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Synthesis of counters with threshold elements
1965
6th Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1965)
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Basic set of logical elements. Implementation of Boolean functions: Look-Up Tables (LUTs), two-level and multilevel circuits. Threshold logic. Boolean function minimization (4 hours). ...
Multi-level logic synthesis (4 hours). Technology independent transformations: decomposition, extraction, factoring, substitution and collapsing. Division of Boolean functions. Reduced ordered BDD. ...
Application of multiplexer as a multipurpose logical element. Synthesis combination schemes by multiplexers usage. Fast arithmetic units design. Carry look ahead adder. ...
doi:10.1109/focs.1965.27
dblp:conf/focs/GustafsonHSW65
fatcat:pytymxniyre4rlzdmfwbck4pfa
Synthesis method of high speed finite state machines
2010
Bulletin of the Polish Academy of Sciences: Technical Sciences
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Elements of two-level minimization are taken into consideration in the state assignment. ...
A number of coding bits, as well as codes for the states, are adjusted to achieve a machine with a determined number of logic levels. ...
The number of logic levels of fast automata must be as few as possible. The logic level extraction problem is solved in the presented approach. ...
doi:10.2478/v10175-010-0067-6
fatcat:jr35zx4u6fda5ipkv7ly55o2ta
Design of Low Power MAX Operator for Multi-valued Logic System
2015
Procedia Computer Science
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A voltage-mode three transistor based MAX circuit for implementation of multi-valued logic (MVL) system is proposed in this paper. ...
The HSpice simulation result confirms the MAX based NOR gate to operate with minimal delay at low power level. The simulations have been performed on 180nm technology. ...
Over the last two decades, synthesis and simplification of logic functions has become a major research field. One of the most upcoming research topics is the multi-valued logic (MVL). ...
doi:10.1016/j.procs.2015.10.067
fatcat:lq763dsw6nfbxcmnvzytyoyvku
Delay optimization using SOP balancing
2011
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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Reducing delay of a digital circuit is an important topic in logic synthesis for standard cells and LUT-based FPGAs. ...
This paper presents a simple, fast, and very efficient synthesis algorithm to improve the delay after technology mapping. ...
As the result of this step, a new structure of two-input ANDs is created. This structure is constructed to minimize the delay while taking into account logic levels of the inputs. ...
doi:10.1109/iccad.2011.6105357
dblp:conf/iccad/MishchenkoBJK11
fatcat:243l6ftqfngbbg32jmntwxwyj4
Power-Efficient And-Exor-Inv Based Realization Of Achilles' Heel Logic Functions
2007
Zenodo
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It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. ...
The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. ...
AND-EXOR-INVERTER REALIZATIONS Most logic synthesis tools use AND and OR gates as basic logic elements, and they derive multi-level logic circuits from AND-OR two-level circuits. ...
doi:10.5281/zenodo.1062237
fatcat:5x2a4pgrzrezlecjnjoghp3v54
Boolean resubstitution with permissible functions and binary decision diagrams
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
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We also applied Boolean resubstitution to our multi-level logic synthesis. ...
Boolean resubstitution is one technique for multi-level logic optimization. Permissible functions are special don't care sets. ...
Two of these techniques used in multi-level logic synthesis are node minimization [2, 4, 5, 61 and transduction methods [l,7] . ...
doi:10.1145/123186.123276
dblp:conf/dac/SatoYMF90
fatcat:62yah3qqsnf2pp53k6bwauv5yu
Methods of improving time efficiency of decomposition dedicated at FPGA structures and using BDD in the process of Cyber-Physical Synthesis
2019
IEEE Access
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INDEX TERMS BDD, cyber-physical synthesis, decomposition, logic synthesis, time efficiency. ...
They include enabling for a quick relocating of variables between bound and free sets, time effective and multilevel technology mapping of multi-output function, and techniques of quick efficiency assessing ...
One of the key elements of a logic synthesis, directed at FPGA, is a decomposition of multi-output functions. ...
doi:10.1109/access.2019.2898230
fatcat:r6jt746dlff7dogsrm2ibattw4
Exploiting fast carry-chains of FPGAs for designing compressor trees
2009
2009 International Conference on Field Programmable Logic and Applications
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The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. ...
This paper demonstrates that the carry chains can be used to build compressor trees, i.e., multi-input addition circuits used for parallel accumulation and partial product reduction for parallel multipliers ...
Um and Kim [12] proposed a layout-aware synthesis method for compressor trees that tries to minimize wirelength between CSAs. ...
doi:10.1109/fpl.2009.5272301
dblp:conf/fpl/Parandeh-AfsharBI09
fatcat:3afp6padfzeldmu7ncugvf5lcq
River PLAs
2002
Proceedings - Design Automation Conference
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These two features make the River PLA a highly predictable structure. Glacier PLAs can be an alternative to FPGAs, but with a simpler and more efficient design methodology. ...
Similar results hold for d OR . The delay computation for GPLAs is the same.
DESIGN METHODOLOGY 4.1. Synthesis of RPLAs
Multi-level logic minimization. ...
The GPLA synthesis algorithm is written in JAVA, except the multi-level logic minimization uses SIS [2] and the SOP minimization uses ESPRESSO [3] . ...
doi:10.1145/513969.513970
fatcat:kfnpk3ssmfgwthxxdkmzct6plu
River PLAs: a regular circuit structure
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
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These two features make the River PLA a highly predictable structure. Glacier PLAs can be an alternative to FPGAs, but with a simpler and more efficient design methodology. ...
Similar results hold for d OR . The delay computation for GPLAs is the same.
DESIGN METHODOLOGY 4.1. Synthesis of RPLAs
Multi-level logic minimization. ...
The GPLA synthesis algorithm is written in JAVA, except the multi-level logic minimization uses SIS [2] and the SOP minimization uses ESPRESSO [3] . ...
doi:10.1109/dac.2002.1012620
fatcat:pzsq2x5cgreytpbcv5dbm4bthq
River PLAs
2002
Proceedings - Design Automation Conference
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These two features make the River PLA a highly predictable structure. Glacier PLAs can be an alternative to FPGAs, but with a simpler and more efficient design methodology. ...
Similar results hold for d OR . The delay computation for GPLAs is the same.
DESIGN METHODOLOGY 4.1. Synthesis of RPLAs
Multi-level logic minimization. ...
The GPLA synthesis algorithm is written in JAVA, except the multi-level logic minimization uses SIS [2] and the SOP minimization uses ESPRESSO [3] . ...
doi:10.1145/513918.513970
dblp:conf/dac/MoB02
fatcat:shzsq32rz5bjdirhxydimk4tey
Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating
2006
Proceedings of the Design Automation & Test in Europe Conference
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A logic synthesis approach for domino/skewed logic styles based on Shannon expansion is proposed, that dynamically identifies idle parts of logic and applies clock gating to them to reduce power in the ...
In this paper, we present a novel low-cost design methodology for reducing clock power in the active mode for dynamic circuits with fine-grained clock gating. ...
Similar to domino logic, skewed logic is operated in prechargeevaluation fashion for high performance with fast transition for evaluation, and slow transition for precharge. ...
doi:10.1109/date.2006.243769
dblp:conf/date/BanerjeeRMB06
fatcat:2y466ymai5eergmht7wumpudoy
Power And Delay Optimized Graph Representation For Combinational Logic Circuits
2007
Zenodo
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In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), ...
Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter ...
The results obtained so far, indicate that NNIG logic data structures are potential candidates for enabling low power, delay and even area optimized compact multi-level combinatorial logic designs and ...
doi:10.5281/zenodo.1077846
fatcat:bip4jc4gmvadtel3ybbpel3qwm
Software synthesis from synchronous specifications using logic simulation techniques
2002
Proceedings - Design Automation Conference
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Specifically, we propose a framework for software synthesis from multi-valued logic, including fast evaluation of logic functions, and scheduling techniques for node execution. ...
It is demonstrated that the logic optimization and simulation techniques can be combined to produce fast execution code for such embedded systems. ...
Acknowledgement The authors would like to acknowledge Max Chiodo for providing an intermediate format and its parser from Esterel DC. ...
doi:10.1145/514001.514002
fatcat:xhbxrvy7rzhsfmonbjmkoyxjuq
Software synthesis from synchronous specifications using logic simulation techniques
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
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Specifically, we propose a framework for software synthesis from multi-valued logic, including fast evaluation of logic functions, and scheduling techniques for node execution. ...
It is demonstrated that the logic optimization and simulation techniques can be combined to produce fast execution code for such embedded systems. ...
Acknowledgement The authors would like to acknowledge Max Chiodo for providing an intermediate format and its parser from Esterel DC. ...
doi:10.1109/dac.2002.1012643
fatcat:hdigrscgwndqjbyvu4o4ywl7by
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