Filters








7,639 Hits in 5.8 sec

Fast Timing Simulation Of Transient Faults In Digital Circuits

A. Dharchoudhury, S.M. Kang, H. Cha, J.H. Patel
IEEE/ACM International Conference on Computer-Aided Design  
Transient fault simulation is an important verication activity for circuits used in critical applications since such faults account for over 80% of all system failures.  ...  This paper presents a timing level transient fault simulator that bridges the gap between electrical and gate-level transient fault simulators.  ...  In this paper, we h a v e presented a new fast timing simulator of transient faults in CMOS digital circuits. Trasient faults are modeled as piecewise quadratic injected current waveforms.  ... 
doi:10.1109/iccad.1994.629902 dblp:conf/iccad/DharchoudhuryKCP94 fatcat:6frjepm3tbdgdiuaeyy3heshoe

Real time digital power system simulator design considerations and relay performance evaluation

D. Jakominich, R. Krebs, D. Retzmann, A. Kumar
1999 IEEE Transactions on Power Delivery  
SVCs, HVDC, ASC and CSC can be modelled fully digital by computer simulation and transient real-time data Injection as well as analog by using physical simulation with original converter controllers for  ...  Highlighting the requirements of a hybrid real-time simulator including the complete spectrum of power system dynamics, this report describes an analog cum digital model used for real-time assessment of  ...  In most of the cases, simulator tests are required to evaluate relay performance for fast tripping under transient condltions; the transient being a result of system faults.  ... 
doi:10.1109/61.772314 fatcat:c6roc7wfnzaf3mvlad6e6rquka

RobuCheck: A Robustness Checker for Digital Circuits

Stefan Frehse, Gorschwin Fey, Andre Suelflow, Rolf Drechsler
2010 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools  
Automated support is required to analyze the fault tolerance of circuits. In this paper, ROBUCHECK is presented -a design tool to analyze the fault tolerance of digital circuits.  ...  Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality.  ...  Fault simulation allows for a fast classification in case of non-robust circuits. In contrast, for very robust circuits the simulation causes an overhead as no components can be classified. B.  ... 
doi:10.1109/dsd.2010.91 dblp:conf/dsd/FrehseFSD10 fatcat:j35vgueqobcqjntdu5en7uuigy

Fast, robust DC and transient fault simulation for nonlinear analogue circuits

Z. R. Yang, M. Zwolinski
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
The need to reduce fault simulation time for has resulted in the research into concurrent analogue fault simulation, analogous to digital fault simulation.  ...  A robust, fast algorithm for concurrent analogue fault simulation is presented in this paper.  ...  fault collapsing is measured by the difference between the fault-free circuit Table 4 4 CPU times in seconds for transient fault simulation of example circuits.  ... 
doi:10.1145/307418.307498 fatcat:ds24aoh2mjbehac4qbbs35w72u

RobuCheck

Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010 Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems - DYADEM-FTS '10  
Automated support is required to analyze the fault tolerance of circuits. In this paper, ROBUCHECK is presented -a design tool to analyze the fault tolerance of digital circuits.  ...  Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality.  ...  Fault simulation allows for a fast classification in case of non-robust circuits. In contrast, for very robust circuits the simulation causes an overhead as no components can be classified. B.  ... 
doi:10.1145/1772630.1772641 fatcat:ho4hr6bv2zex5n72juau4a3ave

Modeling and simulation of the power transformer faults and related protective relay behavior

M. Kezunovic, Yong Guo
2000 IEEE Transactions on Power Delivery  
The modeling of power transformer faults and its application to performance evaluation of a commercial digital power transformer relay are the objective of this study.  ...  The computer simulation results presented in this paper are consistent with the laboratory test result obtained using an analog power system model.  ...  ACKNOWLEDGMENT The assistance of Prof. D. Chen and W. Chen of Huazhong University of Science and Technology is most appreciated. The test data collected by them in EPDL made this study possible.  ... 
doi:10.1109/61.847227 fatcat:442dgdgi2rfqzifi2vc43fbhfu

Comparative Analysis of Time and Physical Redundancy Techniques for Fault Detection

Namita Arya, Amit Prakash Singh
2017 Indonesian Journal of Electrical Engineering and Computer Science  
Time required during testing is a main factor for the cost of a chip. This time is directly proportional to the number of testing in the circuitry. So the test set should be very small.  ...  This aspect of compaction has motivated the work present here with some methods of fault detection and avoidance techniques via redundancy logic as Time redundancy and physical redundancy.</p>  ...  This technique is very helpful to catch whether the circuit is error free or not. AK. Jameil introduces a digital circuit testing simulator named as deductive fault simulator in [4] .  ... 
doi:10.11591/ijeecs.v6.i1.pp66-71 fatcat:wioilb7kgjgpber7iaywckss4a

Key Technologies Development of Transient Signals Based Protection Device Using DSP and S-Transform

Xingmao Liu, Gao Zheng
2017 IOP Conference Series: Materials Science and Engineering  
In order to further introduce the dynamic simulation experiments for the transient signal based protection algorithm, the key technologies of transient signal based protection device were developed.  ...  The correctness of new principle of transient signal based protection used to be verified by simulating.  ...  Acknowledgments This work was supported in part by the project (16ZB0215) supported by educational commission of Sichuan province of China and in part by the project (KYTZ201624) supported by the Scientific  ... 
doi:10.1088/1757-899x/199/1/012131 fatcat:4u66sanjwfck3aek5n37uc7vau

CONCERT

Junwei Hou, Abhijit Chatterjee
1998 Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98  
Between successive time steps, all circuits in the fault list are simulated concurrently before the simulator proceeds to the next time step.  ...  Three primary techniques in CONCERT, including fault ordering, state prediction, and reduced-order fault matrix computation, greatly simplify fault simulation by making use of the residual similarities  ...  In the analog domain, no fast fault simulation techniques have been reported for nonlinear circuits under general transient stimulus.  ... 
doi:10.1145/288548.289058 dblp:conf/iccad/HouC98 fatcat:yfvnhspf5ndbbpbkac22e5s4zq

Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

M Fazeli, S N Ahmadian, S G Miremadi, H Asadi, M B Tahoori
2011 2011 Design, Automation & Test in Europe  
In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs).  ...  MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches.  ...  CONCLUSIONS In this paper, we proposed a very fast and accurate analytical technique for SER estimation of digital circuits in the presence of METs.  ... 
doi:10.1109/date.2011.5763020 dblp:conf/date/FazeliAMAT11 fatcat:4mrixmm46beojh3ikby65vn47q

Prediction of Short-Term Voltage Instability Using a Digital Faster than Real-Time Replica

Arun Joseph, Milos Cvetkovic, Peter Palensky
2018 IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society  
We show that, using a digital faster than real-time replica, the FIDVR event can be detected in required time and that the transient voltage deviation index (TVDI) can be quickly calculated.  ...  This article presents methods for predictive analysis of Fault Induced Dynamic Voltage Recovery (FIDVR) event using a faster than real-time digital replica of a power system.  ...  in the Real-Time Digital Simulator (RTDS) with RSCAD software.  ... 
doi:10.1109/iecon.2018.8592818 dblp:conf/iecon/JosephCP18 fatcat:hxuzpspwxjdudmfliz6azam6mi

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

H Hashempour, J Dohmen, Bratislav Tasić, B Kruseman, C Hora, M van Beurden, Yizi Xing
2011 2011 Design, Automation & Test in Europe  
We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process.  ...  A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time.  ...  Examples of fast fault simulators for transient analysis in linear circuits are DRAFTS and FLYER [13] [14] .  ... 
doi:10.1109/date.2011.5763065 dblp:conf/date/HashempourDTKHBX11 fatcat:sssigwylfbgq5dcz7t7xdhz3g4

Laser-Induced Fault Simulation

Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013 2013 Euromicro Conference on Digital System Design  
This paper presents a multi-level simulator for laser-induced fault simulation in digital circuits.  ...  The paper mainly focuses on multi-level simulation for obtaining high accuracy of the fault simulation at transistor level and high speed for the simulation of the rest of the circuit.  ...  The region is defined by the actual fault sites plus some digital levels forward in the circuit.  ... 
doi:10.1109/dsd.2013.72 dblp:conf/dsd/LuNFR13 fatcat:7onv3s5bqnau3lbc4iwlscniv4

Performance Analysis of Transient Fault-Injection and Fault-Tolerant System for Digital Circuits on FPGA

Sharath Kumar Y N, Dinesha P
2020 International Journal of Advanced Computer Science and Applications  
In this work, an efficient Transient Fault-Injection system (FIS) and Fault-Tolerant System (FTS) are designed for digital circuits.  ...  A Fault-Tolerant System is necessary to improve the reliability of digital circuits with the presence of Fault Injection and also improves the system performance with better Fault Coverage.  ...  The power utilization of all digital circuits in the FIS-FTS module is in the range of 0.086 to 0.092W, which is quite less and suitable real-time FTS based digital circuits. B.  ... 
doi:10.14569/ijacsa.2020.0110516 fatcat:tyjczfj6sjcztk2er3pjz2zhx4

Measurement of very Fast Transient over Voltages by using MATLAB in a 2-phase various Gas Insulated Substations

M. Kondalu, P. S. Subramanyam
2013 International Journal of Computer Applications  
Measurement of very fast transient over voltages due to single line to ground fault in a 3-phase various gas insulated substations (132KV, 220KV, 400KV).  ...  This Paper deals with MATLAB circuits are develop to purpose for the components of various voltages of Gas Insulated Substations (132KV, 220KV, 400KV) and very fast transient over voltages are calculated  ...  CONCLUSION: The fast transient over voltages are obtained due to switching operation of single line to ground fault in 3-phase system are studied.  ... 
doi:10.5120/12526-9163 fatcat:vodfn4upbjafldulbvymtdcitm
« Previous Showing results 1 — 15 out of 7,639 results