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Fast complete memory consistency verification

Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
This paper proposes a novel fast memory consistency verification method by identifying a new natural partial order: time order.  ...  The verification of an execution against memory consistency is known to be NP-hard.  ...  In this paper, we propose a fast and easy-to-generalize memory consistency verification method.  ... 
doi:10.1109/hpca.2009.4798276 dblp:conf/hpca/ChenLHCSWP09 fatcat:uqt534rbajh6rmnkvpqvj5rf7e

Fast and Generalized Polynomial Time Memory Consistency Verification [article]

Amitabha Roy, Stephan Zeisset, Charles J. Fleckenstein, John C. Huang
2006 arXiv   pre-print
The problem of verifying multi-threaded execution against the memory consistency model of a processor is known to be an NP hard problem.  ...  These are often used in practice for microprocessor verification. We present a low complexity and fully parallelized algorithm to check program execution against the processor consistency model.  ...  Acknowledgments: We would like to thank our colleagues Jeffrey Wilson and Sreenivasa Guttal for their contribution to the tool, Mrinal Deo and Harish Kumar for their assistance with memory consistency  ... 
arXiv:cs/0605039v4 fatcat:qrom3ktsy5g2njjo65oumrh57q

Fast construction of test-program generators for digital signal processors

S. Rubin, M. Levinger, R.R. Pratt, W.P. Moore
1999 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258)  
This paper describes a work-model for the fast, low cost construction of a test-program generator for DSPs.  ...  Test-program generators play a key role in hardware functional verification of large scale processors.  ...  The definition of a legal test, in this case, is a test-program that is completely consistent with the architecture's specification.  ... 
doi:10.1109/icassp.1999.758317 dblp:conf/icassp/RubinLPM99 fatcat:k23xgqnhcferhkpdhwlptwtzjy

Verification of chip multiprocessor memory systems using a relaxed scoreboard

Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz
2008 2008 41st IEEE/ACM International Symposium on Microarchitecture  
Verification of chip multiprocessor memory systems remains challenging.  ...  We demonstrate the use of the relaxed scoreboard in verifying RTL implementations of two different memory models, Transactional Coherency and Consistency (TCC) and Relaxed Consistency, for up to 32 processors  ...  Acknowledgment The authors would like to thank the rest of the Stanford Smart Memories faculty and team, including Don Stark, Kyle Kelley, Zain Asgar, Wajahat Qadeer and Rehan Hameed, for their assistance  ... 
doi:10.1109/micro.2008.4771799 dblp:conf/micro/ShachamWSFRH08 fatcat:ztcj5eg77vax3cvtmnwlj5gh24

LEVER: A Tool for Learning Based Verification [chapter]

Abhay Vardhan, Mahesh Viswanathan
2006 Lecture Notes in Computer Science  
For some examples, the analysis could not be completed either because the tool did not terminate in two hours, or it exhausted available memory, or (in the case of ALV) it reported that it cannot provide  ...  Lever FAST BRAIN ALV noaccel 0.031s ↑ 0.004s 0.025s flatcounter 0.153s ↑ 0.004s 0.052s manufacturing 0.821s 2.422s 10.974s ↑ ticket2i 0.585s 0.679s ↑ ↑ consistency 0.932s 142.814s 0.057s  ... 
doi:10.1007/11817963_43 fatcat:4cfwwhjmijecxkd53n53mgycq4

McVerSi: A test generation framework for fast memory consistency verification in simulation

Marco Elver, Vijay Nagarajan
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
The memory consistency model (MCM), which formally specifies the behaviour of the memory system, is used by programmers to reason about parallel programs.  ...  We propose McVerSi, a test generation framework for fast MCM verification of a full-system design implementation under simulation.  ...  We provide a simulator-independent C++ library (including consistency model descriptions, checker, and test generator):  ... 
doi:10.1109/hpca.2016.7446099 dblp:conf/hpca/NagarajanE16 fatcat:2qj22lyclvb2bl2l4pvp476liu

HW/SW co-verification of embedded systems using bounded model checking

Daniel Groβe, Ulrich Kühne, Rolf Drechsler
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
In this paper we present an integrated approach for formal verification of hardware and software. The approach is demonstrated on a RISC CPU. The verification is based on bounded model checking.  ...  In this context formal verification techniques allow to prove the functional correctness. But in embedded system design the integration of software components becomes more and more important.  ...  For an embedded system, that in our context consists of digital components without analog units, a complete verification can be performed.  ... 
doi:10.1145/1127908.1127920 dblp:conf/glvlsi/GrosseKD06 fatcat:kzgy6cbvefgjblyqtsh2uagube

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking

Daniel Grosse, Ulrich Kuhne, Rolf Drechsler
2005 International Workshop on Microprocessor Test and Verification  
In this paper we present an integrated approach for formal verification of hardware and software. The approach is demonstrated on a RISC CPU. The verification is based on bounded model checking.  ...  In this context formal verification techniques allow to prove the correctness. But in embedded system design the integration of software components becomes more and more important.  ...  In the following the complete verification of the hardware, interface and assembler programs for the RISC CPU is discussed.  ... 
doi:10.1109/mtv.2005.12 dblp:conf/mtv/GrosseKD05 fatcat:yvg5jdtu3vds3f24vribe52rbu

Unified HW/SW Co-Verification Methodology for High Throughput Wireless Communication System

Nana Sutisna, Reina Hongyo, Leonardo Lanante Jr., Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi
2016 IPSJ Transactions on System LSI Design Methodology  
., MATLAB or C/C++) and physical level verification (e.g., FPGA). It allows performing fast HW/SW verification, as well as fast turn-around design exploration.  ...  Moreover, the proposed verification platform can be used for complete characterization of communication performance of a MIMO wireless system employing MLD MIMO decoder for various operation modes and  ...  Software Design The software design mainly consist of three layers which are: ( 1 ) System level simulation of complete wireless communication system in MATLAB.  ... 
doi:10.2197/ipsjtsldm.9.61 fatcat:onwiyrgeevbmbc4uxj4euqiroi

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

Yuichi Nakamura, Kouhei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump"  ...  This method enables easy debugging, rich portability, and high verification speed, at a low cost.  ...  For example, a waveform viewer for signals internal to the FPGA and a memory system has been completed.  ... 
doi:10.1145/996566.996655 dblp:conf/dac/NakamuraHKYY04 fatcat:qjyead4p25f6plnyuzg7noot7e

Development of an Approach to Automatic Test Generation Based on the Graph Model of a Cache Hierarchy

Anton V. Garashchenko, Larisa G. Gagarina, Kyaw Zaw Ye, Ekaterina Dorogova, Maria Kochneva
2020 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)  
RELATED WORK The cache memory of heterogeneous SoC is an intermediate fast buffer with the most frequently used data from less high-speed types of memory.  ...  The methodology for generating verification tests consists of generating corresponding meta-language instructions in a graph model.  ... 
doi:10.1109/eiconrus49466.2020.9039334 fatcat:r4u5oqngzfft3daafvb5be2bpm

Proving Properties of Concurrent Programs [chapter]

Gerard J. Holzmann
2013 Lecture Notes in Computer Science  
likely eventually exhaust available memory and abandon the search without completing the task.  ...  The system we developed consisted of 16 small networked computers, each running at 500 MHz.  ... 
doi:10.1007/978-3-642-39176-7_2 fatcat:3x2fm544mzf3hf6og52g6zlg5q

Test environment for verification of multi-processor memory subsystem unit

D.A. Lebedev, M.V. Petrochenkov
2019 Proceedings of the Institute for System Programming of RAS  
State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency.  ...  In this paper, we present some approaches for verification of memory subsystem units of multi-core microprocessors.  ...  Unfortunately, the speed of memory access is not growing as fast as the speed of the processor [1] . Thus, one of the biggest bottleneck elements become the memory subsystem.  ... 
doi:10.15514/ispras-2019-31(3)-6 fatcat:5oqz33mkibfnrnoilwgiu455yi

Formal Verification of Designs with Complex Control by Symbolic Simulation [chapter]

Gerd Ritter, Hans Eveking, Holger Hinrichsen
1999 Lecture Notes in Computer Science  
The verification tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall verification  ...  Having reached the end of both descriptions with consistent decisions, a complete path is found and the verification goal is checked for this path, e.g., if both produce the same final values of r.  ...  The formal verification technique presented in this paper uses symbolic simulation. Employing symbolic values makes the complete verification of all cases possible.  ... 
doi:10.1007/3-540-48153-2_18 fatcat:xikff34jmzcjpc3gwqqvo5azfy

Formal Verification Of Cache System Using A Novel Cache Memory Model

Guowei Hou, Lixin Yu, Wei Zhuang, Hui Qin, Xue Yang
2015 Zenodo  
In the paper, a formal model checking verification flow is suggested and a new cache memory model which is called "exhaustive search model" is proposed.  ...  Formal verification is proposed to ensure the correctness of the design and make functional verification more efficient.  ...  They theoretically promise a very fast verification time and 100% coverage.  ... 
doi:10.5281/zenodo.1099783 fatcat:uwjpsnfc65eghmjeryukl7px7y
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