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Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA

Thiem Van Chu, Shimpei Sato, Kenji Kise
2015 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines  
in open-loop simulations Network on Chip (NoC) On-chip communication backbone C R Core Router Our Approach Fast and accurate emulation of large NoC designs on a single FPGA Emulation  ...  two methods to enable fast and accurate emulation of large-scale NoC architectures on a single FPGA 2745x simulation speedup over Booksim is achieved when emulating an 128x128 NoC design with the state-of-the-art  ... 
doi:10.1109/fccm.2015.35 dblp:conf/fccm/ChuSK15 fatcat:tyrjc4jnsba3dk2fwmqfz7r2ou

AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation

Swapnil Lotlikar, Vinayak Pai, Paul V. Gratz
2011 2011 24th Internatioal Conference on VLSI Design  
This paper presents the design, implementation and evaluation of AcENoCs, a flexible and cycle-accurate FPGA emulation platform for validating synchronous and GALS-based NoC architectures.  ...  The key to the successful realization of such architectures is a flexible, fast and robust emulation platform.  ...  In order to meet processing demands, current SoC designs incorporate a large number and a wide variety of IP cores on a single chip.  ... 
doi:10.1109/vlsid.2011.46 dblp:conf/vlsid/LotlikarPG11 fatcat:xwiod2d3xbgsbgj5m3spxybqqu

EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs [article]

Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph
2022 arXiv   pre-print
Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling compared to slow simulations.  ...  In other words, both a fast and flexible design framework is required.  ...  When using only a single FPGA, one can directly map the NoC (if the FPGA is large enough) or use time-division multiplexing (TDM).  ... 
arXiv:2206.11613v1 fatcat:wxakooegcjekrb3lpbiylihowy

Automated modeling and emulation of interconnect designs for many-core chip multiprocessors

Colin J. Ihrig, Rami Melhem, Alex K. Jones
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
This paper presents the ACME design automation tool flow that facilitates the hardware emulation of newly proposed large multi-core interconnection networks on FPGAs to mitigate the slowdowns of single  ...  Our results demonstrate that for 16-core and 64-core cycle accurate packet switching networks, the FPGA-based emulation is faster than Simics-based software simulation by 2.5x and 14.6x, respectively.  ...  For simulations requiring detailed/cycle accurate results from the network-on-chip, the network component dominates the time of the system simulation.  ... 
doi:10.1145/1837274.1837383 dblp:conf/dac/IhrigMJ10 fatcat:gtga2dbv2ferhdzoyzzwyvr2ei

DART

Danyao Wang, Natalie Enright Jerger, J. Gregory Steffan
2011 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip - NOCS '11  
The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems  ...  a large FPGA design.  ...  Acknowledgements This research was supported by the Natural Science and Engineering Research Council (NSERC). We thank Jason Anderson and Andreas Moshovos for their feedback on this work.  ... 
doi:10.1145/1999946.1999970 dblp:conf/nocs/WangJS11 fatcat:pdsncvrtsbdwxp5udj5vhr6hi4

DART: A Programmable Architecture for NoC Simulation on FPGAs

2014 IEEE transactions on computers  
The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems  ...  a large FPGA design.  ...  Acknowledgements This research was supported by the Natural Science and Engineering Research Council (NSERC). We thank Jason Anderson and Andreas Moshovos for their feedback on this work.  ... 
doi:10.1109/tc.2012.121 fatcat:utp3dgsyrjfovogo2j3ea5ghr4

Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution

R.B. Mouhoub, O. Hammami
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
The proposed approach is validated on a 4 way multiprocessor on chip design space exploration where a 6 order of magnitude improvement have been achieved over cycle accurate simulation.  ...  Prohibitive simulation time of single multiprocessor configuration makes large design space exploration impossible without massive use of computing resources and still implementation issues are not tackled  ...  These evaluations have been cycle-accurate after actual implementation on single chip large scale FPGA devices.  ... 
doi:10.1109/ipdps.2006.1639623 dblp:conf/ipps/MouhoubH06 fatcat:oeagswclb5fgpksaucl3nvz7wa

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Pablo Del Valle, David Atienza, Ivan Magan, Javier Flores, Esther Perez, Jose Mendias, Luca Benini, Giovanni Micheli
2006 2006 IFIP International Conference on Very Large Scale Integration  
In this paper, we present a new FPGA-based emulation framework that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level.  ...  With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread.  ...  This work is partially supported by the Spanish Government Research Grant TIN2005-05619 and a Mobility Post-Doc Grant from UCM for David Atienza.  ... 
doi:10.1109/vlsisoc.2006.313218 dblp:conf/vlsi/ValleAMFPMBM06 fatcat:22g34hntvnfvnno2vhyx7nl6qu

RAMP: Research Accelerator for Multiple Processors

John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
2007 IEEE Micro  
INTRODUCTION In 2005 there was a historic change of direction in the computer hardware industry: All microprocessor companies announced that their future products would be single-chip multiprocessors,  ...  However, the rate of such innovation is currently slowed by the following traditional development cycle: 1) It takes approximately four years and many millions of dollars to prototype a new architecture  ...  Special thanks to Xilinx for their continuing financial support and donation of FPGAs, and development tools.  ... 
doi:10.1109/mm.2007.39 fatcat:uhezfqyvgfgwba6ly4d32obqua

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA

Jintao Zheng, Ning Wu, Gaizhen Yan, Fen Ge, Lei Zhou
2015 IEICE Electronics Express  
The design method of RcEF3Ns employs a single FPGA to manage vertical transaction independently, supporting bus and network communication mechanism.  ...  Taking advantage of Three Dimension (3D) Integrated Circuit (IC) technology, 3D Network-on-Chip (NoC) is becoming a promising architecture of high-performance System-on-Chip (SoC).  ...  Fast and accurate performances evaluation for 3D NoC is therefore becoming a critical issue.  ... 
doi:10.1587/elex.12.20150065 fatcat:p57br4tf2fbyzbh3xyf2nkkx7i

Leveraging latency-insensitivity to ease multiple FPGA design

Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind Mithal, Joel Emer
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
Acknowledgements: During the course of this work, Kermin Fleming was supported by the Intel Graduate Fellowship.  ...  On a single FPGA, HAsim scales to 16 cores before the FPGA runs out of resources.  ...  In particular, large HAsim models need large amounts of fast memory.  ... 
doi:10.1145/2145694.2145725 dblp:conf/fpga/FlemingAPPME12 fatcat:pbenduxl3ncijaiyuknrbqnkda

Implementation of BEE

Chen Chang, Kimmo Kuusilinna, Brian Richards, Robert W. Brodersen
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific  ...  Although real-time emulation of arbitrarily fast ASIC designs is impractical, designs with a clock frequency below 60 MHz can be prototyped using the current FPGA technology.  ...  INTRODUCTION With the increasing complexity and integration of digital and analog systems, the computing power required for detailed cycle accurate and bit-true software simulation of even a single subsystem  ... 
doi:10.1145/611817.611832 dblp:conf/fpga/ChangKRB03 fatcat:jiyy4c3uefh7xjwsmi3iw2hzvq

Implementation of BEE

Chen Chang, Kimmo Kuusilinna, Brian Richards, Robert W. Brodersen
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific  ...  Although real-time emulation of arbitrarily fast ASIC designs is impractical, designs with a clock frequency below 60 MHz can be prototyped using the current FPGA technology.  ...  INTRODUCTION With the increasing complexity and integration of digital and analog systems, the computing power required for detailed cycle accurate and bit-true software simulation of even a single subsystem  ... 
doi:10.1145/611831.611832 fatcat:blksbyxv2bh3dpmp5q5l65aqra

An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

Xinyu Li, Omar Hammami
2009 International Journal of Reconfigurable Computing  
Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements.  ...  The Triple Data Encryption Standard (TDES) cryptographic algorithm on a 48-PE single-chip distributed memory multiprocessor is selected as an application example of the flow.  ...  a Network-on-Chip.  ... 
doi:10.1155/2009/631490 fatcat:kcrbtxmc7jgd3jptwwrxqcuqf4

3D NoC emulation model on a single FPGA

Jonathan D'Hoore, Poona Bahrebar, Dirk Stroobandt
2020 Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop  
Networks-on-Chip (NoCs) have emerged as a promising solution for the communication crisis in large and highly interconnected Systems-on-Chip.  ...  However, the FPGA-based NoC emulators proposed so far are mostly limited to 2D NoCs. In this paper, we extend the 2D FNoC emulation model to 3D using a single FPGA.  ...  The resulting 3D FNoC emulator enables fast and accurate emulation of 3D NoCs with up to thousands of nodes on a single FPGA.  ... 
doi:10.1145/3414622.3431910 fatcat:vipih7dnenb2tlib3jbwsjttmu
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