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Fast priority queues for cached memory

Peter Sanders
2000 ACM Journal of Experimental Algorithmics  
doi:10.1145/351827.384249 fatcat:5elwbti5preclpfojioqdys7iu

Speeding-up exact and fast FIFO-based cache configuration simulation

Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2011 IEICE Electronics Express  
Recently, the CRCB method has been proposed for LRU-based (Least Recently Used-based) cache configuration simulation, which can calculate cache hit/miss counts accurately and very fast changing the three  ...  In this paper, we propose a speeding-up cache configuration simulation method for embedded applications that uses FIFO as a cache replacement policy.  ...  Kurata Memorial Hitachi Science and Technology Foundation.  ... 
doi:10.1587/elex.8.1161 fatcat:ciwcrk75qnc3tmo5xbkjhzt77e

Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems

Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011 IPSJ Transactions on System LSI Design Methodology  
In this paper, we propose exact and fast L1 cache configuration simulation algorithms for embedded applications that use PLRU or FIFO as a cache replacement policy.  ...  An extremely fast cache configuration simulation method, CRCB (Configuration Reduction approach by the Cache Behavior), has been recently proposed which can calculate cache hit/miss counts accurately for  ...  Since Properties 5 and 6 just discuss a general priority queue, they hold true for priority queues mapped from PLRUt trees.  ... 
doi:10.2197/ipsjtsldm.4.166 fatcat:mzh572gsszbjzdetda7bw5in2e

Memory Hierarchy Aware Parallel Priority Based Data Structures

Dinesh Agarwal
2011 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum  
A vast majority of scientific applications require a priority based data structure to discriminate among available data elements; for instance, a priority based data structure is imperative for extracting  ...  Traditional priority based data structures are tree-based that makes them cache unfriendly due to the exponentially increasing distance between parent and child nodes.  ...  On the contrary, a parallel priority queue facilitates fast access to k top-priority elements, where k is an application dependent constant.  ... 
doi:10.1109/ipdps.2011.372 dblp:conf/ipps/Agarwal11 fatcat:udqldaia4ra5xbvt7jljqjf5li

An Empirical Study of Cache-Oblivious Priority Queues and their Application to the Shortest Path Problem [article]

Benjamin Sach, Raphaël Clifford
2008 arXiv   pre-print
Our results show that when RAM is limited and data is swapping to external storage, the Cache-Oblivious priority queues achieve orders of magnitude speedups over standard internal memory techniques.  ...  In recent years the Cache-Oblivious model of external memory computation has provided an attractive theoretical basis for the analysis of algorithms on massive datasets.  ...  Acknowledgment The authors would like to thank Ashley Montanaro for helpful comments on the final draft.  ... 
arXiv:0802.1026v1 fatcat:662tevtdira7to2ywjnhsgy7im

Efficient Two-Level Scheduling for Concurrent Graph Processing [article]

Jin Zhao
2018 arXiv   pre-print
Secondly, multiple priority-based data scheduling provides the support of prioritized iteration for concurrent jobs, which is based on the global priority generated by individual priority of each job.  ...  memory.  ...  The Pri of each priority queue is assigned from q to 1, so we accumulate the Pri of each block in whole priority queues as the priority value for the global priority queue, e.g., for is 2q-1.  ... 
arXiv:1806.00777v1 fatcat:vgx6zoio55df3ekpsjtc3wws2a

CAMP

Shahram Ghandeharizadeh, Sandy Irani, Jenny Lam, Jason Yap
2014 Proceedings of the 15th International Middleware Conference on - Middleware '14  
Similar to an implementation of LRU using queues, it adapts to changing workload patterns based on the history of requests for different key-value pairs.  ...  Cost Adaptive Multi-queue eviction Policy (CAMP) is an algorithm for a general purpose key-value store (KVS) that manages key-value pairs computed by applications with different access patterns, key-value  ...  GDS requires an internal priority queue to determine a key-value pair to evict from the cache.  ... 
doi:10.1145/2663165.2663317 dblp:conf/middleware/GhandeharizadehILY14 fatcat:vx7xck57c5aiffeakpqvv2r6ie

Cache-oblivious priority queue and graph algorithm applications

Lars Arge, Michael A. Bender, Erik D. Demaine, Bryan Holland-Minkley, J. Ian Munro
2002 Proceedings of the thiry-fourth annual ACM symposium on Theory of computing - STOC '02  
Priority queues are a critical component in many of the best known external-memory graph algorithms, and using our cache-oblivious priority queue we develop several cacheoblivious graph algorithms. *  ...  The bounds match the bounds of several previously developed external-memory (cache-aware) priority queue data structures, which all rely crucially on knowledge about M and B.  ...  [25] developed optimal cache-oblivious algorithms for matrix multiplication, matrix transposition, Fast Fourier Transform, and sorting.  ... 
doi:10.1145/509948.509950 fatcat:fhzfr2w4pbexzngwdtygse57tu

Cache-oblivious priority queue and graph algorithm applications

Lars Arge, Michael A. Bender, Erik D. Demaine, Bryan Holland-Minkley, J. Ian Munro
2002 Proceedings of the thiry-fourth annual ACM symposium on Theory of computing - STOC '02  
Priority queues are a critical component in many of the best known external-memory graph algorithms, and using our cache-oblivious priority queue we develop several cacheoblivious graph algorithms.  ...  The bounds match the bounds of several previously developed external-memory (cache-aware) priority queue data structures, which all rely crucially on knowledge about M and B.  ...  [25] developed optimal cache-oblivious algorithms for matrix multiplication, matrix transposition, Fast Fourier Transform, and sorting.  ... 
doi:10.1145/509907.509950 dblp:conf/stoc/ArgeBDHM02 fatcat:fmrm5cem4jbizlv7tbl37oz2wm

Scavenger: A New Last Level Cache Architecture with Global Block Priority

Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jose Martinez
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
and on average (geometric mean) 14.2% for nine memory-bound SPEC 2000 applications.  ...  In this paper, we present Scavenger, a new architecture for last-level caches.  ...  We thank Vijay Degalahal for helping us with HSPICE, and Jugash Chandarlapati for developing the leakage energy model.  ... 
doi:10.1109/micro.2007.42 dblp:conf/micro/BasuKKCM07 fatcat:4wuxz6mqcjh4hhywwemfy2x26i

An Efficient Multiprocessor Memory Management Framework Using Multi-Agents

Sarath Chandran K R
2012 Computer Science & Engineering An International Journal  
The current generation computer users call for fast addressal of their requests.  ...  The coordinated processing of programs face challenges in areas of process scheduling, memory allocation and effective use of level caches due to dynamic variation of resource availed and used.  ...  Cache buffers data between the fast processor and slow main memory. Its goal is to minimize the number of processor accesses to main memory.  ... 
doi:10.5121/cseij.2012.2606 fatcat:nuy4owqk45fkjinn6y5m6f5m2m

DCA: A DRAM-cache-Aware DRAM Controller

Cheng-Chieh Huang, Vijay Nagarajan, Arpit Joshi
2016 SC16: International Conference for High Performance Computing, Networking, Storage and Analysis  
Since the DRAM cache can be orders of magnitude larger than a conventional SRAM cache, the size of its cache tags can also be large.  ...  However, this increases the complexity of a DRAM cache request, which now translates into multiple DRAM cache accesses (tag/data). In this work, we address how to schedule these DRAM cache accesses.  ...  ACKNOWLEDGEMENTS We would like to thank Boris Grot and the anonymous reviewers for their helpful comments.  ... 
doi:10.1109/sc.2016.75 dblp:conf/sc/HuangNJ16 fatcat:bostt5yotvctdpneiu5vpd2rfe

Scavenger: A New Last Level Cache Architecture with Global Block Priority

Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jose Martinez
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
and on average (geometric mean) 14.2% for nine memory-bound SPEC 2000 applications.  ...  In this paper, we present Scavenger, a new architecture for last-level caches.  ...  We thank Vijay Degalahal for helping us with HSPICE, and Jugash Chandarlapati for developing the leakage energy model.  ... 
doi:10.1109/micro.2007.4408273 fatcat:cgcf5aeekff7jcg5drqwpawvvi

The Power of Priority: NoC Based Distributed Cache Coherency

Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007 First International Symposium on Networks-on-Chip (NOCS'07)  
The low cost Priority-based NoC is extremely useful for increasing performance of almost any other CMP transaction (i.e. uncached and cache-coherenet R/W, search in DNUCA, isolating low priority traffic  ...  We address previously proposed CMP architectures based on Non Uniform Cache Architecture (NUCA) over NoC, analyze basic memory transactions and translate them into a set of network transactions.  ...  The processor interface is responsible for packetizing the local CPU L2 memory transactions, enqueing them in the source queue and scheduling the queue for transmission over the network not before receiving  ... 
doi:10.1109/nocs.2007.42 dblp:conf/nocs/BolotinGCGK07 fatcat:vofomf4eavcgtlcl3po6i2jcga

An On-Demand Retrieval Method Based on Hybrid NoSQL for Multi-Layer Image Tiles in Disaster Reduction Visualization

Linyao Qiu, Qing Zhu, Zhiqiang Du, Meng Wang, Yida Fan
2017 ISPRS International Journal of Geo-Information  
The traditional tile retrieval method for visualization cannot distinguish between distinct layers and traverses all image datasets for each tile query.  ...  For instance, in the process of flood reduction, the basic disaster environmental visualization requires 1 km spatial resolution for daily monitoring [15] .  ...  The order of tile retrieval in the cache depends on the access priority of queues, and the history queue has the lowest priority.  ... 
doi:10.3390/ijgi6010008 fatcat:nf4g3nrc4vfl3motspsbtevybq
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