A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2011; you can also visit the original URL.
The file type is application/pdf.
Filters
Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture
2010
IEICE transactions on electronics
Preserved Fulltext
Subsequently, we present a parallel FFT architecture targeted for multi-core platforms computing systems. ...
Results show that the parallel FFT implementation on SmartCell is about 14.9 and 2.7 times faster than network-on-chip (NoC) and Mor-phoSys implementations, respectively. ...
Fast Fourier Transform (FFT) is a fast DFT algorithm that reduces the computing complexity from O(N 2 ) to O(Nlog 2 (N)). ...
doi:10.1587/transele.e93.c.407
fatcat:yyp7gzjxszd2dovpktt2bkp55a
Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture
2009
2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2011; you can also visit the original URL.
The file type is application/pdf.
Subsequently, we present a parallel FFT architecture targeted for multi-core platforms computing systems. ...
Results show that the parallel FFT implementation on SmartCell is about 14.9 and 2.7 times faster than network-on-chip (NoC) and Mor-phoSys implementations, respectively. ...
Fast Fourier Transform (FFT) is a fast DFT algorithm that reduces the computing complexity from O(N 2 ) to O(Nlog 2 (N)). ...
doi:10.1109/asap.2009.33
dblp:conf/asap/LiangH09
fatcat:pexuxp5drvarbbytajb3frjr5q
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
2007
Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2008; you can also visit the original URL.
The file type is application/pdf.
As a case study, a novel reconfigurable FFT architecture is presented and modelled in SystemC. Power, area and performance figures are presented as well. ...
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. ...
As a result of that Fast Fourier Transform (FFT) is used, which is an efficient algorithm for computation of the DFT. ...
doi:10.1109/ahs.2007.102
dblp:conf/ahs/AhmadiniaAA07
fatcat:mfefwnjzxnfybcg77t7vdq26pi
Selected Papers from ReConFig 2008
2009
International Journal of Reconfigurable Computing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
The development, exploration, and validation methodology of real-time operating systems for reconfigurable Systems-on-Chip is covered in "OveRSoC: a framework for the exploration of RTOS for RSoC platforms ...
The fourth edition of the International Conference on Reconfigurable Computing and FPGAs (ReConFig 2008) was held in Cancun, Mexico, from December 3 to 5, 2008. ...
The development, exploration, and validation methodology of real-time operating systems for reconfigurable Systems-on-Chip is covered in "OveRSoC: a framework for the exploration of RTOS for RSoC platforms ...
doi:10.1155/2009/869329
fatcat:zqfusxerbfehlaaycfy47dofly
A Survey Of Baseband Architecture For Software Defined Radio
2016
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
This paper is a survey of recent works that proposes a baseband processor architecture for software defined radio. A classification of different approaches is proposed. ...
A dedicated processor for FFT calculation is designed in [7] to meet the requirement of FFT computation for different wireless standards. ...
A reconfigurable architecture design based on FPGA is mentioned in [30] . ...
doi:10.5281/zenodo.1126159
fatcat:mdhjmvmfafdarg7m6uezpuxiei
High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing Platform
2006
2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Other Versions
The processing consists of computation of power, its average and peak, over a set of input values. This platform sustains simultaneous data streams on each of the four input channels. ...
In this paper, we present our design of a FPGA based reconfigurable platform for high performance power-spectrum analysis. ...
based addon signal analyzer card, or (3) by digitizing experimental data and performing a Fast Fourier Transform (FFT) on a desktop machine. ...
doi:10.1109/reconf.2006.307786
dblp:conf/reconfig/AbhyankarSASP06
fatcat:y7hn3wih55eold5anqaxhpkuh4
Review on Scalable FFT Architecture for High Speed Communication Standard
2015
International Journal of Science and Research (IJSR)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
The Fast Fourier transform (FFT) has presently a key role in signal processing applications. Most of the system needs high flexibility, high speed and high efficiency. ...
The baseband hardware should be economical and capable enough to compute FFT within the time constraints necessary to support multiple wireless standards. ...
A FFT ASIP has been implemented on Tensilica's reconfigurable processor platform. ...
doi:10.21275/v4i11.nov151544
fatcat:ekfhjxfbu5gbtjlemgnqyvjz6u
Run-Time Reconfigurable FFT Engine
2010
مجلة النهرين للعلوم الهندسية
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
The system employs sixteen reconfigurable parallel FFT cores. Each core represents a 16 complex point parallel FFT processor, running in continuous realtime FFT engine. ...
This paper develops a system level architecture for implementing a cost-efficient, FPGA-based realtime FFT engine. ...
Finally, Kamalizad et al [19] , mapped the FFT to the MorphoSys reconfigurable computing platform to achieve high performance FFT architecture. ...
doaj:a3cd7a3bea89464595260e3dc19e4672
fatcat:v6x4hexgv5ahlnmhmr7a73huti
Reconfigurable and Reusable Mutual Module Based Parameterization Approach for DWT and FFT Algorithm
2014
Research Journal of Applied Sciences Engineering and Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
But in this study, it is proposed a reconfigurable FFT (Fast Fourier Transform) operator using the common operator approach. ...
This operator can be reconfigured to switch from an operator dedicated to compute the FFT to an operator which computes the FFT in order to perform DWT. ...
With the fast and growing interest in VLSI technology, various techniques have been presented on FPGA platform to improve the performance of the embedded hardware. ...
doi:10.19026/rjaset.7.855
fatcat:4rxrs6rjibh3tkccda5jkf2yle
Guest Editorial: Design and Implementation of DSP Systems
2016
Journal of Signal Processing Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Results for 1D, 2D, and 3D FFTs show that their designs can achieve close to the theoretical peak performance on several different platforms. ...
The experimental results show that the run-time technique can achieve higher instruction-level parallelism compared to a 16-issue VLIW processor. ...
We would also like to offer thanks to the anonymous reviewers for their role in ensuring a high quality review process and our appreciation to Courtney Dramis for her help. ...
doi:10.1007/s11265-016-1167-9
fatcat:c2k4zwhgqba55orharpm6ladqq
Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications
2008
2008 IEEE Computer Society Annual Symposium on VLSI
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2012; you can also visit the original URL.
The file type is application/pdf.
IEEE Computer Society Annual Symposium on VLSI 978-0-7695-3170-0/08 $25.00 ...
A case study of a system consisting of a LEON processor, a reconfigurable FFT and a reconfigurable Viterbi decoder is considered with the option of system scalability for future upgrades. ...
Reconfigurable FFT Model The implemented FFT block is based on a radix-2 algorithm and can be reconfigured for different FFT sizes from 16-points to 2048-points. ...
doi:10.1109/isvlsi.2008.55
dblp:conf/isvlsi/AhmadiniaAA08
fatcat:ewjuq6wbrvfnzafdpcm3k2hgva
Efficient architecture mapping of FFT/IFFT for cognitive radio networks
2014
2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
A common module in these standards is the fast Fourier transform (FFT) and its inverse. ...
In this paper, we propose a highly flexible FFT/IFFT architecture that can support a broad variety of transform sizes and efficient mapping to programmable testbed platforms for cognitive radio networks ...
Liang and Huang proposed the mapping algorithm for parallel FFT into SmartCell, a coarse-grained reconfigurable architecture [2] . ...
doi:10.1109/icassp.2014.6854339
dblp:conf/icassp/WangYCCBT14
fatcat:ou6wxathd5dwroaqiztyri4gci
Transmuter
2020
Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
This is facilitated by a fabric of light-weight cores connected to a network of reconfigurable caches and crossbars. ...
Transmuter adapts to changing kernel characteristics, such as data reuse and control divergence, through the ability to reconfigure the on-chip memory type, resource sharing and dataflow at run-time within ...
The material is based on research sponsored by Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650-18-2-7864. The U.S. ...
doi:10.1145/3410463.3414627
dblp:conf/IEEEpact/PalFPKAYHBMXKMS20
fatcat:kwsaun2g65b6jl6mdqrhgiv7yq
Reconfigurable Embedded Architectures for On-Board Synthetic-Aperture Radar Processing
2021
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
Single and multi-core implementations are discussed, as well as the computation of approximations for the most time-consuming operations of the algorithm. ...
SAR systems designed for on-board space environments present different challenges when compared to other systems. ...
ACKNOWLEDGMENT This work was supported by national funds through Fundação para a Ciência e a Tecnologia (FCT), under grants with references UIDB/50021/2020 (INESC-ID multi-annual funding) and project SARRROCA ...
doi:10.5281/zenodo.5090024
fatcat:f3bemazkdbftdckdpnzwjyumcu
A Novel Architecture for Different DSP Applications Using Field Programmable Gate Array
2016
International Journal of Microelectronics Engineering
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
The proposed processor is based on parallel re-configurable which is implemented on FPGA. ...
This paper presents a reconfigurable processor for different digital signal processing applications. ...
Reconfigurable Architecture with BBU Fig.
FPGA IMPLEMENTATION This section describes the design, implementation, and verification of the proposed reconfigurable architecture on an FPGA platform. ...
doi:10.5121/ijme.2016.2202
fatcat:53l3lfr5nbc2bn3ik2xblq2cim
« Previous
Showing results 1 — 15 out of 2,237 results