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Unified HW/SW Co-Verification Methodology for High Throughput Wireless Communication System

Nana Sutisna, Reina Hongyo, Leonardo Lanante Jr., Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi
2016 IPSJ Transactions on System LSI Design Methodology  
As complexity of system LSI design is increased significantly, efficient verification methodology is mandatory to achieve reliable system and to speed up development time.  ...  It allows performing fast HW/SW verification, as well as fast turn-around design exploration.  ...  Hence, reliable design and fast time-tomarket of large scale system can be achieved.  ... 
doi:10.2197/ipsjtsldm.9.61 fatcat:onwiyrgeevbmbc4uxj4euqiroi

Area Efficient Rapid Signal Acquisition scheme for High Doppler DSSS Signals

D. Karunakar Reddy, T. Satya Savithri
2013 International Journal of Computer Networks & Communications  
The advanced design practices in FPGAs are used to achieve resource sharing and high clock speed of operation.  ...  A new scheme for PN code phase delay estimation with correlation of differential signals, followed by precise Doppler estimation using Fast Fourier Transform (FFT) is presented.  ...  ACKNOWLEDGMENT The authors acknowledge the support received from ECE department, JNTU Hyderabad for reviewing the work and providing the R&D infrastructure.  ... 
doi:10.5121/ijcnc.2013.5206 fatcat:qvql4rbiurhclctpwawjffsllq

Advanced digital receiver principles and technologies for PCS

H. Meyr, R. Subramanian
1995 IEEE Communications Magazine  
The synergy between digital radio communications and VLSI signal processing is revolutionizing the design of wireless terminals.  ...  Driving this synergy are certain fundamental paradigms in modern communication theory, digital signal processing, and VLSI design.  ...  They include the advances and availability of low-cost, high-speed A/D converters, ever-increasing levels of integration, higher priceiperformance value, lower manufacturing costs, greater flexibility,  ... 
doi:10.1109/35.339884 fatcat:kk2zmvkkdjhsji43p3sbags6aa

2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29

2021 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages.  ...  ., +, TVLSI Nov. 2021 1861-1874 C C language Global Analysis of C Concurrency in High-Level Synthesis.  ... 
doi:10.1109/tvlsi.2021.3136367 fatcat:fwqswbyzejgfhgbzywrvsf2qgi

VLSI Architecture for MB-OFDM Transmitter

Priyanka Hedaoo, Dr. U. M. Gokhale, Prof. Shweta Thakur
2014 IOSR Journal of VLSI and Signal processing  
In this paper introduced the structure of MB-OFDM system transmitter and the design of transmitter baseband based on FPGA is described in detail.  ...  MB-OFDM) Multi-Band Orthogonal Frequency Division Multiplexing is a suitable solution for implementation of high speed data transmission in ultra wideband spectrum by dividing the spectrum into available  ...  higher integration and design flexibility and the technical line for the implementation of MB-OFDM transmitter baseband module with Xilinx Virtex II series FPGA is introduced in this paper.  ... 
doi:10.9790/4200-04321422 fatcat:fyxxnbcvzneqhhmvhxzlb3isua

Towards a highly flexible spectrum sensing platform for cognitive radio networks

Peter Lohmiller, Ahmed Elsokary, Vaclav Valenta, Xiaolei Gai, Andreas Trasser, Hermann Schumacher, Sebastien Chartier
2012 2012 International Symposium on Signals, Systems, and Electronics (ISSSE)  
The design and implementation status of the system will be described, as well as its validation under realistic noise and interference conditions, sensing white spaces in the UHF TV band.  ...  Yet its commercially viable implementation requires compact, low-cost, flexible sensing receivers.  ...  ACKNOWLEDGMENT The authors would like to thank Cassidian for valuable discussions and IHP for fabrication of the chip.  ... 
doi:10.1109/issse.2012.6374345 dblp:conf/issse2/LohmillerEVGTSC12 fatcat:cefxfueqpvczxhi5ljyynrtfsm

WiLIS: Architectural modeling of wireless systems

Kermin Elliott Fleming, Man Cheuk Ng, Samuel Gross, Arvind
2011 (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE  
This requirement coupled with the heavy computation typical of most physical-layer processing, rules out pure software solutions.  ...  In this paper we describe WiLIS, an FPGA-based hybrid hardwaresoftware system designed to facilitate the development of wireless protocols.  ...  Without a flexible, high-speed simulator like WiLIS, the rapid evaluation of these designs would not have been possible.  ... 
doi:10.1109/ispass.2011.5762736 dblp:conf/ispass/FlemingNGA11 fatcat:k2vw3oboxbhtpnnajxh4sbleye

A Versatile Variable Rate LDPC Codec Architecture

Colm P. Fewer, Mark F. Flanagan, Anthony D. Fagan
2007 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
This versatility also allows the LDPC system to be used in a variety of applications since the encoder and decoder can be used with codes that span a wide range of lengths and rates.  ...  This paper presents a system architecture for low-density parity-check (LDPC) codes that allows dynamic switching of LDPC codes within the encoder and decoder without hardware modification of these modules  ...  This unified architecture of code, encoder and decoder yields a practical high-speed codec implementation for LDPC codes while providing a very high level of versatility. II.  ... 
doi:10.1109/tcsi.2007.904641 fatcat:hg6rumlmynaeddeqvhef4cskam

Wideband Digital Channelizer based on Spectrum Sensing

Bindu H M, Kiran A Gupta
2020 2020 Third International Conference on Advances in Electronics, Computers and Communications (ICAECC)  
The filter bank is designed for 10Mhz bandwidth with 32 sub-band channels. A 32-point IFFT block is used with both real and imaginary inputs and outputs.  ...  It is one of the most critical component in a communication receiver system. This paper presents an extensive study on different techniques of channelizing and spectrum sensing for cognitive radio.  ...  It is also called as flexible architecture radio [4] .  ... 
doi:10.1109/icaecc50550.2020.9339512 fatcat:i4hwwskjh5duzihkownf2oukhe

IEEE 802.11n Physical Layer Implementation on Field Programmable Gate Array

Hendra Setiawan, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi
2012 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
Kata kunci: IEEE 802.11n, lapisan fisik, Model Based Design, RTL, FPGA Abstract Register transfer level (RTL) development is a time cost step that requires high diligence and fidelity to get the valid  ...  The result of this research is a prototyping FPGA StratixII EP2S180 that has properly worked as a 2x2 MIMO WLAN with maximum throughput 144 Mbps.  ...  The WLAN standard high-speed and high-reliability, IEEE802.11n [2] , which enhanced with the previous standards IEEE802.11a/b/g, can achieve maximum throughput more than 100 Mbps in both Medium Access  ... 
doi:10.12928/telkomnika.v10i1.761 fatcat:hpnulceb2jghldkrgqireap6wu

IEEE 802.11n Physical Layer Implementation On Field Programmable Gate Array

Hendra Setiawan, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi
2012 TELKOMNIKA Indonesian Journal of Electrical Engineering  
Kata kunci: IEEE 802.11n, lapisan fisik, Model Based Design, RTL, FPGA Abstract Register transfer level (RTL) development is a time cost step that requires high diligence and fidelity to get the valid  ...  The result of this research is a prototyping FPGA StratixII EP2S180 that has properly worked as a 2x2 MIMO WLAN with maximum throughput 144 Mbps.  ...  The WLAN standard high-speed and high-reliability, IEEE802.11n [2] , which enhanced with the previous standards IEEE802.11a/b/g, can achieve maximum throughput more than 100 Mbps in both Medium Access  ... 
doi:10.11591/telkomnika.v10i1.655 fatcat:j6amapu7kfcg5f6mcmt7ohym6y

IEEE 802.11n Physical Layer Implementation On Field Programmable Gate Array

Hendra Setiawan, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi
2012 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
Kata kunci: IEEE 802.11n, lapisan fisik, Model Based Design, RTL, FPGA Abstract Register transfer level (RTL) development is a time cost step that requires high diligence and fidelity to get the valid  ...  The result of this research is a prototyping FPGA StratixII EP2S180 that has properly worked as a 2x2 MIMO WLAN with maximum throughput 144 Mbps.  ...  The WLAN standard high-speed and high-reliability, IEEE802.11n [2] , which enhanced with the previous standards IEEE802.11a/b/g, can achieve maximum throughput more than 100 Mbps in both Medium Access  ... 
doi:10.12928/telkomnika.v10i1.141 fatcat:w7oz523n45d4rcs5dm5muiav5e

Energy-efficient LDPC codec design using cost-effective early termination scheme

Cheng-Hung Lin, Yuan-Syun Wu, Chen-Pei Song
2019 IET Computers & Digital Techniques  
Compared with the other decoder chips, the prototyping codec operating at 278 MHz achieves the best decoding energy efficiency of 156 pJ/bit with a high decoding throughput of 4.3 Gbps.  ...  The prototyping codec also achieves a high encoding throughput of 4.4 Gbps.  ...  Acknowledgments This work is supported in part by Ministry of Science and Technology, Taiwan, under grants MOST 106-2221-E-155-060 and MOST 105-2221-E-155-074.  ... 
doi:10.1049/iet-cdt.2018.5074 fatcat:566asqfjrvgyjenofqd5drthea

FPGA-based design of an evolutionary controller for collision-free robot navigation

M. A. H. B. Azhar, K. R. Dimond
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
This paper describes how area-performance tradeoffs can be performed quickly at the high-level using a behavioral synthesis tool called AccelFPGA which reads in highlevel descriptions of DSP applications  ...  With the introduction of advanced FPGA architectures which provide built-in DSP support such as the Xilinx Virtex-II, and the Altera Stratix, a new hardware alternative is available for DSP designers.  ...  In this scheme, we include a novel implementation of an additive white Gaussian noise (AWGN) generator with high speed and high accuracy for channel emulator.  ... 
doi:10.1145/611817.611852 dblp:conf/fpga/AzharD03 fatcat:juups7gn3ve2vhw2fbicwvt5kq

Lattice adaptive filter implementation for FPGA

Zdenek Pohl, Rudolf Matoušek, Jirí Kadlec, Milan Tichý, Miroslav Lícko
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
This paper describes how area-performance tradeoffs can be performed quickly at the high-level using a behavioral synthesis tool called AccelFPGA which reads in highlevel descriptions of DSP applications  ...  With the introduction of advanced FPGA architectures which provide built-in DSP support such as the Xilinx Virtex-II, and the Altera Stratix, a new hardware alternative is available for DSP designers.  ...  In this scheme, we include a novel implementation of an additive white Gaussian noise (AWGN) generator with high speed and high accuracy for channel emulator.  ... 
doi:10.1145/611817.611877 dblp:conf/fpga/PohlMKTL03 fatcat:vg523unfzvcmvl2rsw4ja3ksma
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