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Fairness Modulo Theory: A New Approach to LTL Software Model Checking [chapter]

Daniel Dietsch, Matthias Heizmann, Vincent Langenfeld, Andreas Podelski
2015 Lecture Notes in Computer Science  
We present a new approach to LTL software model checking (i.e., to statically analyze a program and verify a temporal property from the full class of LTL including general liveness properties) which aims  ...  The idea is to select finite prefixes of a path and check these for infeasibility before considering the full infinite path.  ...  In this paper, we introduce an approach to LTL software model checking which is based on fairness modulo theory, an extension of reachability modulo theory as introduced by Lal and Qadeer [42] .  ... 
doi:10.1007/978-3-319-21690-4_4 fatcat:fbisyn7olve6rj76nbcfdtgjzu

Applying Formal Methods to Networking: Theory, Techniques, and Applications

Junaid Qadir, Osman Hasan
2015 IEEE Communications Surveys and Tutorials  
The lack of formalization of the Internet architecture meant limited abstractions and modularity, especially for the control and management planes, thus requiring for every new need a new protocol built  ...  Fortunately, recent work in the space of clean slate Internet design---especially, the software defined networking (SDN) paradigm---offers the Internet community another chance to develop the right kind  ...  A major drawback of model checking approach is the need to create a correct working environment model-this restrictions makes model checking infeasible for many networking verification tasks [148] and  ... 
doi:10.1109/comst.2014.2345792 fatcat:oc6l6pn4tnddjbbr5v4gbbuycq

Rewriting Logic Semantics and Verification of Model Transformations [chapter]

Artur Boronat, Reiko Heckel, José Meseguer
2009 Lecture Notes in Computer Science  
We use a model of a distributed mutual exclusion algorithm to illustrate the approach.  ...  Due to the graph-theoretic nature of models, the theory of graph transformation systems and its technological support provide a convenient environment for formalizing and verifying model transformations  ...  The semantic mapping Ê, when applied to admissible model transformations, plays a crucial role to model check invariants and LTL properties.  ... 
doi:10.1007/978-3-642-00593-0_2 fatcat:6i4gmdhqwrbqxn7c26zqq26sa4

Twenty Years of Rewriting Logic [chapter]

José Meseguer
2010 Lecture Notes in Computer Science  
This paper provides a gentle, intuitive introduction to its main ideas, as well as a survey of the work that many researchers have carried out over the last twenty years in advancing: (i) its foundations  ...  ; (ii) its semantic framework and logical framework uses; (iii) its language implementations and its formal tools; and (iv) its many applications to automated deduction, software and hardware specification  ...  As already mentioned, I feel a debt of gratitude to the many gifted researchers who have made important contributions to the rewriting logic research program.  ... 
doi:10.1007/978-3-642-16310-4_2 fatcat:ho7s76r67nc63bndpoptbh5k4e

Twenty years of rewriting logic

José Meseguer
2012 The Journal of Logic and Algebraic Programming  
This paper provides a gentle, intuitive introduction to its main ideas, as well as a survey of the work that many researchers have carried out over the last twenty years in advancing: (i) its foundations  ...  ; (ii) its semantic framework and logical framework uses; (iii) its language implementations and its formal tools; and (iv) its many applications to automated deduction, software and hardware specification  ...  As already mentioned, I feel a debt of gratitude to the many gifted researchers who have made important contributions to the rewriting logic research program.  ... 
doi:10.1016/j.jlap.2012.06.003 fatcat:5tx4a5uxlvapfpf5fajozkbboi

Model checking

Edmund M. Clarke, E. Allen Emerson, Joseph Sifakis
2009 Communications of the ACM  
CEGAR is used in many software Model Checkers including the SLAM Project at Microsoft [1].  ...  Model Figure 6: The CEGAR Loop for sequential circuits called the localization reduction, which was developed by R.  ...  The automata-theoretic approach to LTL Model Checking is described in [44] .  ... 
doi:10.1145/1592761.1592781 fatcat:4gjaorwdd5a25jeyoyethnw3fy

The nuXmv Symbolic Model Checker [chapter]

Roberto Cavada, Alessandro Cimatti, Michele Dorigatti, Alberto Griggio, Alessandro Mariotti, Andrea Micheli, Sergio Mover, Marco Roveri, Stefano Tonetta
2014 Lecture Notes in Computer Science  
systems, safety assessment, and software model checking.  ...  For infinitestate systems, it extends the NUSMV language with new data types, namely Integers and Reals, and it provides advanced SMT-based model checking techniques.  ...  In this paper we describe NUXMV, a new symbolic model checker for finite-and infinite-state synchronous fair transition systems.  ... 
doi:10.1007/978-3-319-08867-9_22 fatcat:loztxxhszbevhcrvydj6y6bitq

FAST: acceleration from theory to practice

Sébastien Bardin, Alain Finkel, Jérôme Leroux, Laure Petrucci
2008 International Journal on Software Tools for Technology Transfer (STTT)  
Fast has proved to perform very well on case studies. This paper describes the tool, from the underlying theory to the architecture choices.  ...  Fast is a tool for the analysis of systems manipulating unbounded integer variables. We check safety properties by computing the reachability set of the system under study.  ...  We are also grateful to Jonathan Billington and Lin Liu for having provided us with the CPN model of the CES service, to Jean-Michel Couvreur for giving us advice for the implementation of shared automata  ... 
doi:10.1007/s10009-008-0064-3 fatcat:3msu4gglojfpbignampzd2fz44

Formal JVM Code Analysis in JavaFAN [chapter]

Azadeh Farzan, José Meseguer, Grigore Roşu
2004 Lecture Notes in Computer Science  
It supports formal analysis of concurrent JVM programs by means of symbolic simulation, breadth-first search, and LTL model checking.  ...  JavaFAN uses a Maude rewriting logic specification of the JVM semantics as the basis of a software analysis tool with competitive performance.  ...  Our approach seems complementary to both of these, in the sense that it provides new formal analysis capabilities, namely search and LTL model checking.  ... 
doi:10.1007/978-3-540-27815-3_14 fatcat:4jha3u5kpff33atwo6ogvws2iu

LTL Model Checking of LLVM Bitcode with Symbolic Data [chapter]

Petr Bauch, Vojtěch Havel, Jiří Barnat
2014 Lecture Notes in Computer Science  
Yet verifying that a system satisfies such specifications is more difficult than verifying safety properties: the recurrence of a specific program state has to be detected.  ...  To evaluate the framework we compare our method with state-of-the-art tools on a set of unmodified C programs.  ...  While they are designed for CTL model checking, they commonly allow verification of LTL by adding fairness constraints.  ... 
doi:10.1007/978-3-319-14896-0_5 fatcat:kuzyxu6h5nb2xcghzv3syqsxli

Parameterized Synthesis [chapter]

Swen Jacobs, Roderick Bloem
2012 Lecture Notes in Computer Science  
The 2012 ACM CCS: [Theory of computation]: Logic, Formal languages and automata theory; [Software and its engineering]: Software organization and properties—Software functional properties—Formal meth  ...  One option would be to consider approaches that compute (approximations of) the reachable states in regular model checking, and try to extend them to a game-based synthesis approach.  ... 
doi:10.1007/978-3-642-28756-5_25 fatcat:jlo3za3fvzgt7nlkfn7v4avxoy

Invariant-driven specifications in Maude

Manuel Roldán, Francisco Durán, Antonio Vallecillo
2009 Science of Computer Programming  
We exploit Maude's reflective capabilities and its properties as a general semantic framework to provide a generic strategy that allows us to execute Maude specifications taking into account user-defined  ...  This work presents a general mechanism for executing specifications that comply with given invariants, which may be expressed in different formalisms and logics.  ...  Given a state S and an LTL formula F , F {S} returns a new formula which is the formula that needs to be checked immediately after state S.  ... 
doi:10.1016/j.scico.2009.03.003 fatcat:xibh57xhxrc6ph4v5gncu4tmzu

Detection of Conflicting Compliance Rules

Francois Hantry, Mohand-Said Hacid, Romuald Thion
2011 2011 IEEE 15th International Enterprise Distributed Object Computing Conference Workshops  
We extend classical boolean conflict driven solver to provide a new temporal conflict driven solver for temporal logic.  ...  In this paper we investigate the problem of extracting temporal unsatisfiable cores in order to detect the inconsistent part of a specification.  ...  Some approaches (e.g., [40] ) use Bounded Model Checking (BMC) and reuse a boolean SAT-solver method to extract cores but get only a partial result.  ... 
doi:10.1109/edocw.2011.57 dblp:conf/edoc/HantryHT11 fatcat:dmvjksvxyvgbxc6tllx25dukdu

Concurrent Software Architectures [chapter]

2005 Software Paradigms  
The thesis proposes the TRACTA model-checking approach for analysis of concurrent systems.  ...  System specifications are typically expressed in some temporal logic or as automata, giving rise to two general approaches to model checking that are used in practice today [Clarke and Wing 96a]: temporal  ...  Acknowledgements First and foremost, I would like to thank my supervisor, Jeff Kramer. Jeff convinced me to leave investment banking and join the group as a Research Associate, some four years ago.  ... 
doi:10.1002/0471703567.ch18 fatcat:bmnxn3yffngxhgumtp2onr5mji

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

Tomás Grimm, Djones Lettnin, Michael Hübner
2018 Electronics  
Model checking verifies properties against a model to prove that the design conforms to the specifications.  ...  Formal Verification (FV) provides methods and techniques to mathematically prove the correctness of a system, such as Theorem Proving [6, 7] and Model Checking [8, 9] and can be adopted early in the development  ...  Acknowledgments: The authors would like to thank the National Council of Scientific and Technological Development of Brazil-CNPq (process 290009/2014-6) for the financial support of this work.  ... 
doi:10.3390/electronics7060081 fatcat:qz4dai4xo5cabkyizvwfabub3u
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