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Yu Ji, Youyang Zhang, Xinfeng Xie, Shuangchen Li, Peiqi Wang, Xing Hu, Youhui Zhang, Yuan Xie
2019 Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '19  
In this paper, we propose a full system stack solution, composed of a reconfigurable architecture design, Field Programmable Synapse Array (FPSA) and its software system including neural synthesizer, temporal-to-spatial  ...  Evaluations show that, compared to one of state-of-the-art ReRAM-based NN accelerators, PRIME, the computational density of FPSA improves by 31x; for representative NNs, its inference performance can achieve  ...  This work was also supported by NSF grant CCF 1500848, 1719160, 1725447, 1730309, 1740352, SRC nCORE NC2766-A, and CRISP, one of six centers in JUMP, a SRC program sponsored by DARPA.  ... 
doi:10.1145/3297858.3304048 dblp:conf/asplos/JiZXLWHZX19 fatcat:rkyenl34bvc4boxbw45f4q7mkq

A Survey on Memory Subsystems for Deep Neural Network Accelerators

Arghavan Asad, Rupinder Kaur, Farah Mohammadi
2022 Future Internet  
Thus, a review of the different memory architectures applied in DNN accelerators would prove beneficial.  ...  First, an overview of the various memory architectures used in DNN accelerators will be provided, followed by a discussion of memory organizations on non-ASIC DNN accelerators.  ...  FPSA is an NN accelerator [25] with ability in memory processing based on the ReRAM technology.  ... 
doi:10.3390/fi14050146 fatcat:4mrod5zmibgxvp6ppevgnpwlqq

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi
2020 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study.  ...  ., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs.  ...  INTERCONNECTS IN ASIC NN ACCELERATORS In this section, we review the most common interconnection architectures for ASIC-based NN accelerators, including arraybased, mesh-based, custom and reconfigurable  ... 
doi:10.1109/jetcas.2020.3022920 fatcat:idqitgwnrnegbd4dhrly3xsxbi

Towards "general purpose" brain-inspired computing system

Youhui Zhang, Peng Qu, Weimin Zheng
2021 Tsinghua Science and Technology  
As a position paper, this article analyzes the existing brain-inspired chips design characteristics and the current so-called "general purpose" application development frameworks for brain-inspired computing  ...  A recent study proposed the concept of "neuromorphic completeness" and the corresponding system hierarchy, which is helpful to determine the capability boundary of brain-inspired computing system and to  ...  set", FPSA [38, 39] , which can give full play to the advantages of Resistive Random Access Memory (ReRAM).  ... 
doi:10.26599/tst.2021.9010010 fatcat:4woqwaawkbbjrn62xpt7rtgrsy

GPTPU: Accelerating Applications using Edge Tensor Processing Units [article]

Kuan-Chieh Hsu, Hung-Wei Tseng
2021 arXiv   pre-print
Neural network (NN) accelerators have been integrated into a wide-spectrum of computer systems to accommodate the rapidly growing demands for artificial intelligence (AI) and machine learning (ML) applications  ...  that NN accelerators enable for applications.  ...  We also owe a debt of gratitude to Christopher Fraser for his excellent copyediting skills.  ... 
arXiv:2107.05473v2 fatcat:tfdvtpczo5ch5otbo474zxxbty