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Digital Hardware Spiking Neuronal Network with STDP for Real-time Pattern Recognition

Yang Xia, Timothée Levi, Takashi Kohno
2020 Journal of Robotics, Networking and Artificial Life (JRNAL)  
Spike Timing Dependent Plasticity (STDP) is a common learning method for Spiking Neural Networks (SNNs).  ...  Equipped with Ethernet Interface, FPGA allows online configuration as well as real-time processing data input and output.  ...  The STDP is a rule for synaptic plasticity that adjusts the strength of synaptic connections (w) based on the relative timing of the spikes in a pre-and post-synaptic neurons.  ... 
doi:10.2991/jrnal.k.200528.010 fatcat:ujrllxl6yrcz7fafbw6u5ziax4

FPGA Implementation of Simplified Spiking Neural Network [article]

Shikhar Gupta, Arpan Vyas, Gaurav Trivedi
2020 arXiv   pre-print
In this paper, a simpler and computationally efficient SNN model using FPGA architecture is described.  ...  The proposed model is validated on a Xilinx Virtex 6 FPGA and analyzes a fully connected network which consists of 800 neurons and 12,544 synapses in real-time.  ...  CONCLUSION In this paper, we described an architecture for Simplified Spiking Neural Network which is implemented on FPGA and optimized for low power embedded applications with real-time learning.  ... 
arXiv:2010.01200v1 fatcat:ou2bvu3q75gphiemrioemjgvhy

Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks

Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday
2018 2018 IEEE Symposium Series on Computational Intelligence (SSCI)  
The proposed architecture has minimal hardware footprints, power dissipation profile and real-time computational capability, enhancing its usability in constrained applications.  ...  On the contrary, due to the capability of modern hardware such as FPGAs, which operates in MHz and GHz range, facilitates real-time and faster-than-real-time simulations of SNNs.  ...  In this work, we overcome the computational overhead of the SNNs using the benefits of real-time hardware computations on FPGAs, utilizing time-multiplexing to design a SPANNER chip.  ... 
doi:10.1109/ssci.2018.8628710 dblp:conf/ssci/JohnsonLMKTHTMH18 fatcat:d7k4aisj35fxbp4jh6tmhcpkjy

PAX: A mixed hardware/software simulation platform for spiking neural networks

S. Renaud, J. Tomas, N. Lewis, Y. Bornat, A. Daouzli, M. Rudolph, A. Destexhe, S. Saïghi
2010 Neural Networks  
dynamic adaptation rules (Spike-Timing Dependent Plasticity).  ...  The neurons and networks are configurable, and are computed in "biological real time" by which we mean that the difference between simulated time and simulation time is guaranted lower than 50µs.  ...  Finally, a PC running a real-time operating system hosts software functions used to compute the plasticity and to update the synaptic weights of the neural network.  ... 
doi:10.1016/j.neunet.2010.02.006 pmid:20434309 fatcat:2dtewzdc3zh3tatompvknggmmq

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday
2018 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)  
The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity.  ...  The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent  ...  The proposed architecture is appropriate for FPGA-based applications running in environments that induce faults in systems, where reliability is crucial.  ... 
doi:10.1109/vlsid.2018.36 dblp:conf/vlsid/JohnsonLMKTHTMH18 fatcat:ovbk4vd7lvbnhjpui2a23i2mve

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

Athul Sripad, Giovanny Sanchez, Mireya Zapata, Vito Pirrone, Taho Dorta, Salvatore Cambria, Albert Marti, Karthikeyan Krishnamourthy, Jordi Madrenas
2018 Neural Networks  
Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports realtime, large-scale, multi-model SNN computation  ...  This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models.  ...  Evidently, if SNAVA 620 As it can be observed from Tables 2 3, current FPGA-based architectures and multicore-based architectures provide SNN simulation to be used as a tool for exploring some of the  ... 
doi:10.1016/j.neunet.2017.09.011 pmid:29054036 fatcat:qair4swatvh3rlndbbxh76ootm

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

Kit Cheung, Simon R. Schultz, Wayne Luk
2016 Frontiers in Neuroscience  
NeuroFlow supports a number of commonly used 20 current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and 21 the spike-timing-dependent plasticity (STDP) rule for  ...  Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core 24 processor, or 2.83 times the speed of GPU-based platforms.  ...  One FPGA handles the computation of 98,304 neurons. Speedup of NeuroFlow with respect to real-time (a) and performance of NeuroFlow in terms of spike delivery rate (b).  ... 
doi:10.3389/fnins.2015.00516 pmid:26834542 pmcid:PMC4712299 fatcat:r733lgxhgjcppcw7rwxuca7x6y

Real-time simulations of networks of Hodgkin–Huxley neurons using analog circuits

Q. Zou, Y. Bornat, J. Tomas, S. Renaud, A. Destexhe
2006 Neurocomputing  
The main problem is that hardware-based connectivity must be built following predefined plasticity and connectivity rules, and that once the hardware is built, it is usually not possible to change its  ...  The traditional dilemma for performing network simulations with analog circuits is the great difficulty of handling the connectivity in hardware.  ...  The computer reads in real-time the spike events from the board, computes synaptic plasticity algorithms, and dispatches the spike signals as inputs to the ASIC neurons, where they will trigger synaptic  ... 
doi:10.1016/j.neucom.2005.12.061 fatcat:ygxf77ruzzflxj6u4xbhrfl4j4

A Large-Scale Spiking Neural Network Accelerator for FPGA Systems [chapter]

Kit Cheung, Simon R. Schultz, Wayne Luk
2012 Lecture Notes in Computer Science  
We design a parallel SNN accelerator for producing large-scale cortical simulation targeting an off-theshelf Field-Programmable Gate Array (FPGA)-based system.  ...  Using only one FPGA, this accelerator is estimated to support simulation of 64K neurons 2.48 times real-time, and achieves a spike delivery rate which is at least 1.45 times faster than a recent GPU accelerator  ...  FPGA and GPUs are two popular platforms for implementation of SNN accelerators due to their inherent parallel computation architecture.  ... 
doi:10.1007/978-3-642-33269-2_15 fatcat:fc6mzmtq2jbbpaqxve5hp2qnmq

Study of real-time biomimetic CPG on FPGA: behavior and evolution

Timothee Levi, Yanchen Guo, Kazuyuki Aihara, Takashi Kohno
2018 Journal of Robotics, Networking and Artificial Life (JRNAL)  
The network implementation architecture operates on a single computation core and in real-time.  ...  We propose a network of several biomimetic CPGs using biomimetic neuron model and synaptic plasticity. This network is implemented on a FPGA (Field Programmable Gate Array).  ...  The network implementation architecture operates on a single computation core. This digital system works in real-time, requires few resources and is low power consumption.  ... 
doi:10.2991/jrnal.2018.4.4.9 fatcat:vokgxtxhxrdx7g62awnvh3wbaq

Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures

Mostafa Rahimi Azghadi, Saber Moradi, Daniel B. Fasnacht, Mehmet Sirin Ozdas, Giacomo Indiveri
2015 ACM Journal on Emerging Technologies in Computing Systems  
representation infrastructures for configuring arbitrary network architectures, while the programmable synaptic efficacy circuits allow the implementation of different types of spike-based learning mechanisms  ...  Hardware implementations of spiking neural networks offer promising solutions for computational tasks that require compact and low-power computing technologies.  ...  The device and setup proposed therefore represent a useful real-time low-power computing platform for exploring the effectiveness of different types of spike-based learning algorithms, validating their  ... 
doi:10.1145/2658998 fatcat:2qi46cgx4nbxtpyqqyngzz5d64

Design and Implementation of Reconfigurable Neuro-Inspired Computing Model on a FPGA

Basutkar Umamaheshwar Venkata Prashanth, Mohammed Riyaz Ahmed
2020 Advances in Science, Technology and Engineering Systems  
The architecture for design at device level offers the best possible design tradeoff for specific processor architectures and development choices.  ...  The proposed algorithm is implemented on Field Programmable Gate Array (FPGA) to develop a neuron model to be utilized in neuromorphic computing system.  ...  Acknowledgment The Authors wish to thank School of ECE, REVA University, Bengaluru, India for providing necessary facilities in carrying out this research work.  ... 
doi:10.25046/aj050541 fatcat:3pfny2go7feu3foe5lvr6po6qi

Spike pattern recognition using artificial neuron and spike-timing-dependent plasticity implemented on a multi-core embedded platform

F. Grassia, T. Levi, E. Doukkali, T. Kohno
2017 Artificial Life and Robotics  
The objective of this work is to use a multi-core embedded platform as computing architectures for neural applications relevant to neuromorphic engineering: e.g. robotics, artificial and spiking neural  ...  Recently it has been shown how spike-timing-dependent plasticity (STDP) can play a key role in pattern recognition.  ...  Spike pattern recognition using artificial neuron and Spike-Timing-Dependent Plasticity implemented on a multi-core embedded platform ACKNOWLEDGMENTS This work was financially supported by the "PHC Sakura  ... 
doi:10.1007/s10015-017-0421-y fatcat:i435ocl35jekfiogwpreyf524m

Biomimetic neural network for modifying biological dynamics during hybrid experiments

Matthieu Ambroise, Stefano Buccelli, Filippo Grassia, Antoine Pirog, Yannick Bornat, Michela Chiappalone, Timothée Levi
2017 Artificial Life and Robotics  
We adopted a neuromorphic board which is able to perform real-time event detection and trigger an electrical stimulation of the BNN.  ...  The ANN used in the following experiments was made up of 20 excitatory neurons with inhibition synapse and with synaptic plasticity to design Central Pattern Generator (CPG).  ...  However, those designs have been realized for computation purposes without taking into account biological real time. We decided to choose FPGA implementation.  ... 
doi:10.1007/s10015-017-0366-1 fatcat:aehudp76nnh33o7ahm4qlzrnva

Energy efficient parallel neuromorphic architectures with approximate arithmetic on FPGA

Qian Wang, Youjie Li, Botang Shao, Siddhartha Dey, Peng Li
2017 Neurocomputing  
To the best of our knowledge, it is the first time that the approximate computing and parallel processing are applied to FPGA based spiking neural networks.  ...  A B S T R A C T In this paper, we present the parallel neuromorphic processor architectures for spiking neural networks on FPGA.  ...  These plastic synapses are able to change their strength based on an adopted biologically-inspired STDP (Spike-timing-dependent plasticity) learning rule [24] .  ... 
doi:10.1016/j.neucom.2016.09.071 fatcat:bsp6x4n6ercsvaewda6p2wqrum
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