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FPGA side-channel receivers

Ji Sun, Ray Bittner, Ken Eguro
2011 Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11  
In this paper, we explore some of the limits of FPGA side-channel communication.  ...  Specifically, we identify a previously unexplored capability that significantly increases both the potential benefits and risks associated with side-channel communication on an FPGA: an in-device receiver  ...  The side-channel can detect and capture the incoming data on the FPGA with its own receiver.  ... 
doi:10.1145/1950413.1950462 dblp:conf/fpga/SunBE11 fatcat:vd6v2wiv3ndojpierjcp4sxb54

Low-Complexity Digital Modem Implementation for High-Speed Point-to-Point Wireless Communications

Hao Zhang, Xiaojing Huang, Y. Jay Guo
2018 2018 18th International Symposium on Communications and Information Technologies (ISCIT)  
The structures and the implementation using field programmable gate array (FPGA) for the transmitter and receiver filters are described in details.  ...  Pre-equalization for reducing the impact of practical channel frequency response can be easily incorporated into the transmitter filter structure.  ...  At the receiver side, the characteristics of the channel can be shown from receiver filters.  ... 
doi:10.1109/iscit.2018.8587919 fatcat:x36qpgoor5blbbfry7pvobrd6m

Security of Cloud FPGAs: A Survey [article]

Chenglu Jin, Vasudev Gohil, Ramesh Karri, Jeyavijayan Rajendran
2020 arXiv   pre-print
However, since the cloud FPGA technology is still in its infancy, the security implications of this integration of FPGAs in the cloud are not clear.  ...  In this paper, we survey the emerging field of cloud FPGA security, providing a comprehensive overview of the security issues related to cloud FPGAs, and highlighting future challenges in this research  ...  Power side-channel [79, 89] , timing side-channel [28, 78] , electromagnetic side-channel [29, 43] , and photonic-emission sidechannel [80, 117] are a few examples of side-channels.  ... 
arXiv:2005.04867v1 fatcat:yr2habmipvfnbn64yvczvapi34

Optimization on fixed low latency implementation of the GBT core in FPGA

K. Chen, H. Chen, W. Wu, H. Xu, L. Yao
2017 Journal of Instrumentation  
The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.  ...  CERN launches the GBT-FPGA project to provide examples in different types of FPGA.  ...  Acknowledgments The authors would like to thank for the original work of the CERN GBT-FPGA group. We also appreciate the help from Frans Schreuder and Andrea Borga at Nikhef.  ... 
doi:10.1088/1748-0221/12/07/p07011 fatcat:utfakbxnxbam7djnvm33ljdomi

Realisation of AWGN Channel Emulation Modules Under SISO and SIMO Environments for 4G LTE Systems

R. Shantha Selva Kumari, Aarti Meena M
2014 International Journal of Wireless & Mobile Networks  
So, a channel emulator using FPGA helps in the testing of transmitter and receiver by providing a test environment that simulates a real-world wireless channel.  ...  The testing of a wireless transmitter and receiver in the real-world channel is tedious.  ...  These values are added with two sets 16 6 Figure 8 . 8 Receiver side architecture of SIMO Figure 10 . 10 Simulation Result of SIMO The Figure 11 .Figure 12 .Figure 13 . 111213 FPGA FPGA FPGA Editor  ... 
doi:10.5121/ijwmn.2014.6603 fatcat:omiqxffeo5ddllt7r3pwlveolu

Multiplexing and DQPSK Precoding of 10.7-Gb/s Client Signals to 107 Gb/s Using an FPGA

H. Song, A. Adamiecki, P. J. Winzer, C. Woodworth, S. Corteselli, G. Raybon
2008 OFC/NFOEC 2008 - 2008 Conference on Optical Fiber Communication/National Fiber Optic Engineers Conference  
X FPGA.  ...  We implemented a real-time DQPSK precoder for 107-Gb/s data, together with a highspeed channel alignment scheme and the required rate adaptation from 10.7 Gb/s to 13.375 Gb/s, on a Xilinx Virtex II Pro  ...  Such an offset is of minor concern on the receive side of an FPGA, where comma-alignment algorithms may be implemented to align the incoming bit streams.  ... 
doi:10.1109/ofc.2008.4528602 fatcat:psmnpjcopbd4rkr6sr77pnh5x4

Demo: A Unified Platform of Free-Space Optics for High-Quality Video Transmission [article]

Hong-Bae Jeon, Hyung-Joo Moon, Soo-Min Kim, Do-Hoon Kwon, Joon-Woo Lee, Sang-Kook Han, Chan-Byoung Chae
2020 arXiv   pre-print
We use a channel emulator that models the turbulence, scintillation, and power attenuation of the FSO channel and the FPGA-based real-time prototype for processing transmitted and received video signals  ...  In this paper, we investigate video signal transmission through an FPGA-based free-space optical (FSO) communication system prototype.  ...  The SDR platform at each transmitter and receiver side consists of a PXIe chassis (PXIe-1082) and FPGA controller modules (PXIe-8880, 8374, 2953R for transmitter and receiver side) [8] .  ... 
arXiv:2005.06954v1 fatcat:wiaehzei6re3npdgrxanxrf6qa

Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAs

Ilias Giechaskiel, Kasper Rasmussen, Jakub Szefer
2019 2019 IEEE 37th International Conference on Computer Design (ICCD)  
The cross-SLR covert channel is characterized analytically and experimentally on five Xilinx Virtex UltraScale+ FPGAs, both locally and on the Amazon and Huawei clouds.  ...  Several configurations of the source transmitters and the sink receivers are tested, including their locations, types, and sizes.  ...  Remote FPGA Attacks Although traditional covert-and side-channel attacks on FPGAs require physical access to the device [34] , [49] , temperature-and voltage-based remote FPGA attacks are possible.  ... 
doi:10.1109/iccd46524.2019.00010 dblp:conf/iccd/GiechaskielRS19 fatcat:iwhajmm6vvhlxjkrpygb3dynnu

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabe Linares-Barranco
2017 IEEE Transactions on Biomedical Circuits and Systems  
The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps.  ...  Flow Control With reference to Fig. 2 , let us assume that we are sending events from the left-side pAER sender (top left of FPGA-1 in Fig. 2 ) to the right-side pAER receiver (top right of FPGA-2 in  ...  On the receiver side it is possible to down-convert the recov- Likewise, similar clocks are generated derived from the Xtal2 oscillator in FPGA-2 PCB.  ... 
doi:10.1109/tbcas.2017.2717341 pmid:28809708 fatcat:hekyjsz6njdhbaqwuyfv5wlmfy

A DMT Modem Prototype for Broadband PLC

J.L. Carmona, F.J. Canete, J.A. Cortes, L. Diez
2006 2006 IEEE International Symposium on Power Line Communications and Its Applications  
The system architecture is based on two Field Programmable Gate-Arrays (FPGA) and a Digital Signal Processor (DSP), in which the transmitter and receiver algorithms have been implemented.  ...  The modulation employed is Discrete MultiTone (DMT) with bit-loading and adaptive equalization to channel selectivity both in frequency and time.  ...  RECEIVER SIDE A block diagram of the FPGA design of the receiver side is shown in Fig. 4 .  ... 
doi:10.1109/isplc.2006.247437 fatcat:xmcstsvcuff6zeg4caeigix3eu

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

Malte Vesper, Dirk Koch, Kizheppatt Vipin, Suhaib A. Fahmy
2016 2016 26th International Conference on Field Programmable Logic and Applications (FPL)  
As we specified the INPUT channel first in the channel list, it will have the channel ID 0. Therefore, we send our data to channel 0 and receive data from channel 1.  ...  To ease the implementation of user logic, we provide parameterizable buffer-FIFOs for the latter case, as well as a buffer for the send-and another FIFO for the receive-side.  ... 
doi:10.1109/fpl.2016.7577334 dblp:conf/fpl/VesperKVF16 fatcat:3fh7whdkovbzlnanmrtb5sypiy

RIFFA 2.0: A reusable integration framework for FPGA accelerators

Matthew Jacobsen, Ryan Kastner
2013 2013 23rd International Conference on Field programmable Logic and Applications  
RIFFA 2.0 uses PCIe to connect FPGAs to a CPU's system bus.  ...  We present RIFFA 2.0, a reusable integration framework for FPGA accelerators.  ...  Additionally, all writes must declare a length so the receiving side knows how much to expect. Each channel is independent and thread safe. RIFFA 2.0 supports up to 12 channels.  ... 
doi:10.1109/fpl.2013.6645504 dblp:conf/fpl/JacobsenK13 fatcat:7s5ayugcdbemzfj3xs4rexttuq

Experimental demonstration of real time receiver for frequency division multiple access PON

R. Bardoux, A. Carer, A. Lebreton, L. Bramerie, P. Scalart, B. Charbonnier
2015 2015 European Conference on Optical Communication (ECOC)  
In this paper, we present for the first time a real time implementation of a FDM receiver in FPGA 1Gbitps in transceiver modules for an ONU and OLT.  ...  We have successfully tested this real time receiver in the Downstream (DS) i.e. at the ONU side and in the Upstream (US) i.e. at the OLT side.  ...  At the OLT side, two RF signals are obtained from the coherent receiver as it is single polarization [7] .  ... 
doi:10.1109/ecoc.2015.7341628 fatcat:gq5p3vwctjdhhdqthfssyrfwim

Temporal alignment of high-speed transmit channels of FPGA

P.J. Winzer, C. Woodworth, F. Fidler, P.K. Reddy, H. Song, A. Adamiecki
2008 Electronics Letters  
The temporal alignment of 17 parallel 10 Gbit/s transmit channels on a Xilinx Virtex II Pro X FPGA is demonstrated.  ...  A scalable alignment algorithm is described that corrects for random multiple-bit offsets among parallel transmit data streams of highspeed I/O-ports on an FPGA, as required for subsequent multiplexing  ...  The same problem is found upon deserialisation (DES) at the receive (RX) side of high-speed I/Os, but a simple comma-alignment procedure can typically be used to guarantee alignment in this case.  ... 
doi:10.1049/el:20082961 fatcat:z4iwawus4nbyhgocxx3ydm5swq

Back-end Electronics for Low Background and Medium Scale Physics Experiments Based on an Asymmetric Network [article]

Denis Calvet
2018 arXiv   pre-print
adequate for the proposed asymmetric network and shows the design of a back-end unit capable of controlling 32 front-end units at up to 12.8 Gbps of aggregate bandwidth using an inexpensive commercial FPGA  ...  The data of virtual channel B are inverted before transmission for easier delineation on the receiver side.  ...  A simple encoder and decoder (DC-balanced) is needed as well as a simple method for virtual channel delineation. It is intended to deserialize data using regular FPGA I/O pins on the back-end side.  ... 
arXiv:1806.07618v1 fatcat:sqhjff5xovhc5dk3dga4yxv3t4
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