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Average interconnection delay estimation for on-FPGA communication links

T.S.T. Mak, P. Sedcole, P.Y.K. Cheung, W. Luk
2007 Electronics Letters  
A new method is presented, and an analytical expression is derived, for average interconnection delay estimation.  ...  This method is directly applicable to predicting the average delay for high-bandwidth communication links implemented on FPGAs.  ...  flow, such as floor-planning [3] .  ... 
doi:10.1049/el:20071342 fatcat:gj7pql6uova4fhpkjqwy2j3fou

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time

F.-J. Veredas, M. Scheppler, H.-J. Pfleiderer
2006 Proceedings of the Design Automation & Test in Europe Conference  
The experimental investigations use a commercial FPGA and industrial benchmarks. LUT-based Programmable Architectures There are two major players in the FPGA market: Xilinx Inc. and Altera Inc.  ...  Several design methodologies have been proposed in recent years for converting an evaluated Field-Programmable Gate-Array (FPGA) prototypedesign into an MPGA.  ...  Zelix MPGA tile Zelix mask-programmable interconnect is planned in the same fashion as the FPGA, i.e. we have a predefined regular interconnect structure.  ... 
doi:10.1109/date.2006.243745 dblp:conf/date/VeredasSP06 fatcat:iugzmwnv4zex3lfcoe2blums6y

Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis

Vinod Pangracious, Habib Mehrez, Zied Marakchi
2013 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)  
In this paper we propose an architectural level interconnect and area optimization solution to minimize TSV count and programmable interconnects without compromising the FPGA performance.  ...  The experimental results from 3D Tree-based FPGA shows a 40% reduction of TSV count, 37% reduction in interconnect area and 28% reduction in power consumption.  ...  The first floorplan consists of the logic units and local interconnections up to level 3. The second floor plan consists of interconnect tree levels 4 and above.  ... 
doi:10.1109/newcas.2013.6573575 dblp:conf/newcas/PangraciousMM13 fatcat:dryos3upjvcgrljo5drkro5vqa

AN APPLICATION SPECIFIC RECONFIGURABLE ARCHITECTURE FOR FAULT TESTING AND DIAGNOSIS: A SURVEY

A.R Kasetwar .
2014 International Journal of Research in Engineering and Technology  
Mainly Interconnect faults, Logical Faults and Delay are the faults which reduces the performance of FPGA.  ...  This is only because of the faults which are occurring in the FPGA at the runtime of the application.  ...  FIG. 4 . 4 A) Floor Plan for First Test Session B) Floor Plan for Second Test Session.  ... 
doi:10.15623/ijret.2014.0302115 fatcat:wz46jziiybb7fevjzmjjmiabu4

Signal processing at 250 MHz using high-performance FPGA's

Brian Von Herzen
1997 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97  
It does require heroic effort in matching the design with the FPGA fabric, including careful placement, pipelining to the layout, and careful planning of exactly how far a signal can travel over the network  ...  GARP, HSRA [see Tsu, et. al. 1999], CHESS, SFRA, Tabula), interconnect retiming, and streaming compute models build out this vision.  ...  It does require heroic effort in matching the design with the FPGA fabric, including careful placement, pipelining to the layout, and careful planning of exactly how far a signal can travel over the network  ... 
doi:10.1145/258305.258313 dblp:conf/fpga/Herzen97 fatcat:yilvzchdhfedfkh2lh4lbpgy6q

Reconfigurable Adaptive Mems Storage for Real Time Data Tuning

D.Manoj Kumar, Jaya Krishna cheedella, J. Sai Nikhil, M. Sai Tharun, TS.Midhun Narayan, G. Bhaskar
2019 Journal of Physics, Conference Series  
The application to be developed here is the development of Hardware based memristor circuit and Memory design in FPGA. By using this we can decrease Area and power consumption.  ...  RECONFIGURABLE devices, a representative of which is field programmable gate array (FPGA), are picking up their notoriety as a method for the integrated system implementation since the nonrecurring designing  ...  Subsequently, they should be planned each time power is provided.  ... 
doi:10.1088/1742-6596/1362/1/012047 fatcat:juj5acf6cbccrdcajib5hkln4m

Exploration of Heterogeneous FPGA Architectures

Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi
2011 International Journal of Reconfigurable Computing  
Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning.  ...  Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.  ...  for upward interconnect.  ... 
doi:10.1155/2011/121404 fatcat:g36imh2u3rhtzlfb5fzmavsfne

Quantifying the Performance of Optoelectronic FPGA's: The Impact of Optical Interconnect Latency [chapter]

J. Dambre, H. Van Marck, J. Van Campenhout
2000 Interconnects in VLSI Design  
We present first estimates of the impact of optical interconnect latency on system performance, for a particular class of OE multi-FPGA architectures.  ...  In this chapter, we address the performance advantage of using optoelectronic area-I/O to realize three-dimensional multi-FPGA architectures.  ...  Interconnects in VLSI Design OE FPGA architectures We consider multi-FPGA architectures that consist of a number of optically interconnected planes, each containing an equal number of FPGA chips.  ... 
doi:10.1007/978-1-4615-4349-7_15 fatcat:k4aiqso3djcvxhlewkpnqa352y

Based on Multi-FPGA Neuron Simulation Hardware Platform

2016 International Journal of Science and Research (IJSR)  
In this paper, we use multi-chip field-programmable gate array (FPGA) chip to build a model of neural information transmission circuit, and through the neurons and neural network analysis to prove the  ...  interconnect device (FPID: Field Programmable Interconnect Devices) Programmable FPGA interconnects between, according to the number used FPID can be divided into fully cross-connect and partial crossbar  ...  This paper discusses the use of multi-chip FPGA simulation hardware platform to build neural network for the study of large nerve planning networks and brain simulation as a foundation.  ... 
doi:10.21275/v5i3.nov162166 fatcat:2kswp64mzjfwxefh33n4qxgn3y

Design and Implementation of a Efficient Router using X Y Algorithm

Geethanjali .N, Rekha K.R.
2021 Indian Journal of Data Communication and Networking  
The proposed configuration dodges the restrictions of transport based interconnection plans which are frequently applied in part progressively reconfigurable FPGA plans. .  ...  The NOC engineering be better over traditional transport, mutual transport plan , cross bar interconnection design intended for on chip organizations.  ...  Incredibly, this is commensurate with energy efficiency of a most un-troublesome standard interconnect on a FPGA-sensitive feature point joins require a 4.7 mJ/GB.  ... 
doi:10.35940/ijdcn.b5009.061321 fatcat:nuwodmsvsbbfblzvuinnqqwbaq

Experiences Teaching Physical Synthesis of FPGAs and ASICs

Don Bouldin, Pradeep Chimakurthy
2007 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07)  
Interconnect delays dominate gate delays in integrated circuits fabricated using 180-nm feature sizes or below.  ...  Experiences teaching students to design competitive FPGAs and ASICs using physical synthesis are described in this paper.  ...  We plan to continue using this two-step approach to enhance the learning experiences of students while preparing them to produce state-of-the-art solutions. Fig. 1 . 1 Fig.1.  ... 
doi:10.1109/mse.2007.39 dblp:conf/mse/BouldinC07 fatcat:p55hkgfyzvcijd52xqli3dpfam

Interconnection lengths and delays estimation for communication links in FPGAs

Terrence Mak, Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008 Proceedings of the tenth international workshop on System level interconnect prediction - SLIP '08  
This paper presents a new stochastic model to predict interconnection lengths of communication links in FPGAs.  ...  Results also show that the proposed model produces reliable predictions of delay and therefore the methodology can be applied to early stage planning and design optimization for communication links.  ...  flow, such as floor-planning [13, 9] .  ... 
doi:10.1145/1353610.1353612 dblp:conf/slip/MakSCL08 fatcat:kqyq5knglzhbhladz3q27ht6ku

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support

Sonda CHTOUROU, Zied MARRAKCHI, Emna AMOURI, Vinod PANGRACIOUS, Mohamed ABID, Habib MEHREZ
2017 Turkish Journal of Electrical Engineering and Computer Sciences  
This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies.  ...  Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits.  ...  In future work, we plan to introduce heterogeneous logic block heterogeneity for logic function optimization.  ... 
doi:10.3906/elk-1506-51 fatcat:2obvd25n4jhxvetdtpfwnrhw6i

Recent Trends and Improvisations in FPGA

M. Joy Daniel, K. Siva Kumar M.E.
2017 IOSR Journal of Electrical and Electronics Engineering  
By System-on-chip development by using FPGA made easy the advancements in optical interconnects, hardware accelerators and controllers.  ...  With the improvements of VLSI design in FPGA, the application areas got wider. The FPGAs architectural developments afford FPGA developers to produce effective devices day-by-day.  ...  Recently, FPGAs supports vertical migration and density migration. In this paper we see some recent developments using FPGA platforms and applications.  ... 
doi:10.9790/1676-1203027177 fatcat:isael7icofgcxosiszjm5k6dv4

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

I Pappas, V Kalenteridis, N Vassiliadis, H Pournara, K Siozios, G Koutroumpezis, K Tatas, S Nikolaidis, S Siskos, D J Soudris, A Thanailakis
2005 Journal of Physics, Conference Series  
A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18µm CMOS technology.  ...  The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform.  ...  The presented FPGA architecture was designed and implemented in STM 0.18µm CMOS technology and future plans include redesign at 0.13.  ... 
doi:10.1088/1742-6596/10/1/086 fatcat:2axziv5rlzdvffbe3rolxyawbu
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