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Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

Vincenzo Conti, Leonardo Rundo, Giuseppe Billeci, Carmelo Militello, Salvatore Vitabile
2018 Energies  
More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard.  ...  Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices  ...  At the application-level, reconfiguration is enabled and managed by the xdevcfg driver provided by Digilent.  ... 
doi:10.3390/en11040739 fatcat:evjp2d35krat3jjsmxqv4o2vj4

Lattice adaptive filter implementation for FPGA

Zdenek Pohl, Rudolf Matoušek, Jirí Kadlec, Milan Tichý, Miroslav Lícko
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
The employment of field programmable gate arrays (FPGAs) to a robot controller is very attractive, since it allows for fast IC prototyping and low cost modifications.  ...  The poster briefly describes the important hardware issues involved with the FPGA based design of an evolutionary robot controller for the collision free navigation of mobile robots In code division multiple  ...  Moreover, new FPGA architectures must be exploited searching low-static-power devices suitable for an actual implementation of our IP on a WSN.  ... 
doi:10.1145/611817.611877 dblp:conf/fpga/PohlMKTL03 fatcat:vg523unfzvcmvl2rsw4ja3ksma

FPGA-based design of an evolutionary controller for collision-free robot navigation

M. A. H. B. Azhar, K. R. Dimond
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
The employment of field programmable gate arrays (FPGAs) to a robot controller is very attractive, since it allows for fast IC prototyping and low cost modifications.  ...  The poster briefly describes the important hardware issues involved with the FPGA based design of an evolutionary robot controller for the collision free navigation of mobile robots In code division multiple  ...  Moreover, new FPGA architectures must be exploited searching low-static-power devices suitable for an actual implementation of our IP on a WSN.  ... 
doi:10.1145/611817.611852 dblp:conf/fpga/AzharD03 fatcat:juups7gn3ve2vhw2fbicwvt5kq

Proceedings of the ASP-DAC 2003. Asia and South Pacific Design Automation Conference 2003 (Cat. No.03EX627)

2003 Conference of Asia and South Pacific Design Automation 2003  
Adaptive Wire Adjustment for Bounded Skew Clock Distribution Network ffaydar Saaied, Dhamin Al-Khalili, Asim Al-Khalili, Mohamed Nekili ................. 243 Power Minimization by Clock Root Gating Qi  ...  Rake Receiver IP for W-CDMA Alessandro Bianco, Alberto Dassatti, Maurizio Martina, Andrea M o h o , Fabrizio Vacca Robust High-Performance Low-Power Carry Select Adder 499 503 A 500-MHz Low-Power  ... 
doi:10.1109/aspdac.2003.1194983 fatcat:obdbe4dwivgsfpbeuvb7s73fpe

Power Visualization, Analysis, and Optimization Tools for FPGAs

Matthew French, Li Wang, Michael Wirthlin
2006 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines  
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization.  ...  These tools leverage an established FPGA design environment, JHDL, that allows design logic and power utilization to be displayed, analyzed, and cross-probed simultaneously at a level of abstraction close  ...  We would also like to thank Tyler Anderson, Kevin Lundgreen, Nathan Rollins, and Welson Sun at Brigham Young University for their assistance with JHDL / EDIF infrastructure.  ... 
doi:10.1109/fccm.2006.58 dblp:conf/fccm/FrenchWW06 fatcat:3wgcc6naq5gv5c7kexaf35wkie

Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision

R. Carmona-Galán, J. Fernández-Berni, Á. Rodríguez-Vázquez, P. Lopez-Martínez, V. M. Brea-Sánchez, D. Cabello-Ferrer, G. Domenech-Asensi, R. Ruiz-Merino, J. Zapata-Pérez
2018 Proceedings of the 12th International Conference on Distributed Smart Cameras - ICDSC '18  
A set of demos showcase the advances at sensor level, in adapted architectures for signal processing and in power management and energy harvesting.  ...  iCaveats is a Project on the integration of components and architectures for embedded vision in transport and security applications.  ...  In addition, computer vision experts and application developers, who work at higher abstraction levels, do not easily handle hardware programming at low level.  ... 
doi:10.1145/3243394.3243707 dblp:conf/icdsc/Carmona-GalanFR18 fatcat:3i5gnwg6wjempjic7e7wt5w5zm

On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions

Florian Wilde, Michael Pehl
2019 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)  
Application to several published PUF designs demonstrates the methods' capabilities. The results prove the need for a high number of samples when the unpredictability of PUFs is tested.  ...  Physical Unclonable Functions (PUFs) are modern solutions for cheap and secure key storage.  ...  The regular waveform generated by the digital clock manager of the FPGA is used for sampling the irregular signal and the resulting bit stream is uploaded to a computer where it is subjected to standard  ... 
doi:10.1109/newcas44328.2019.8961298 dblp:conf/newcas/WildeP19 fatcat:wv67uzuqlvcmhma3nahzdrr2ta

Subframe multiplexing for FPGA manufacturing test configuration

Erik Chmelar
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
By having this FPGA co-simulation option, some of the IP cores in an FPGA system can be co-simulated, there by freeing up processing power on the host-PC for further developments in a system.  ...  This design utilizes 99% of the FPGA's logical resources and operates at a clock rate of 25 MHz.  ...  The target running frequency of this FPGA is 10GHz. Clock repeaters are added for improved clock distribution.  ... 
doi:10.1145/968280.968315 dblp:conf/fpga/Chmelar04 fatcat:bkkwooxvszbvlfrg4b7h5svtvi

Advanced photonic and electronic systems WILGA 2016

Ryszard S. Romaniuk
2016 International Journal of Electronics and Telecommunications  
Young Researchers Symposium WILGA on Photonics Applications and Web Engineering has been organized since 1998, two times a year.  ...  Subject area of the Wilga Symposium are advanced photonic and electronic systems in all aspects: theoretical, design and application, hardware and software, academic, scientific, research, development,  ...  Key parameters include reference clock recovery and distribution. VHDL based parameterized clock manager simulator for FPGA is under development.  ... 
doi:10.1515/eletel-2016-0042 fatcat:r6s5ba2yxfc7lmi5dede3wfvli

Rack-scale Computing (Dagstuhl Seminar 15421)

Babak Falsafi, Tim Harris, Dushyanth Narayanan, David A. Patterson, Marc Herbstritt
2016 Dagstuhl Reports  
In addition, we require support from hardware for synchronized clocks and to able to inspect remote memory, tap into the network, and replay.  ...  potentially significant modifications to the system and application software stack. 15421 -Rack-scale Computing Discussion notes Data is outgrowing compute power, 2% of world power is being spent in  ...  ., near memory processing) and allow for programmable I/O are desired. Integrated FPGAs on the sockets can bring flexibility for processors in a rack.  ... 
doi:10.4230/dagrep.5.10.35 dblp:journals/dagstuhl-reports/FalsafiHNP15 fatcat:n2i2d5gh5zc4bbvjz7q4iborki

Frank chang recognized for modern cell phone technology and WLAN systems

Mau-Chung Frank Chang
2006 IEEE Solid-State Circuits Society Newsletter  
UCLA and IBM show a low power (5 mW at 6 Gbps) receiver for short-haul applications.  ...  Clock (CSAC) total clock power goal (which implies a ceiling of ~10m W for the physics package alone).  ...  The annual Workshop on Compact Device Modeling for RF/Microwave Applications organized by TU-Delft follows the conference on Wednesday.  ... 
doi:10.1109/n-ssc.2006.6500129 fatcat:72ur4mgqvjeizf4tfsrudwgeaa

Table of contents

2018 2018 IEEE International Frequency Control Symposium (IFCS)  
Products include high-performance and radiationhardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions  ...  Abstract: Electronic Warfare) systems. Its technology is used for a wide range of terrestrial and space applications.  ...  Systems (MEMS) for timing applications.  ... 
doi:10.1109/fcs.2018.8597465 fatcat:xae4twa36bb4bepfweljv2x5sa

Accessible near-storage computing with FPGAs

Robert Schmid, Max Plauth, Lukas Wenzel, Felix Eberhardt, Andreas Polze
2020 Proceedings of the Fifteenth European Conference on Computer Systems  
Secondly, we provide an integrated build process for FPGA overlay images that starts with the acquisition of compute kernels through a package manager and finally allows to dynamically configure near-storage  ...  be made accessible to users and applications.  ...  Acknowledgements We thank the anonymous reviewers and our shepherd, Tim Harris, for their valuable feedback.  ... 
doi:10.1145/3342195.3387557 dblp:conf/eurosys/SchmidPWEP20 fatcat:ykijhsup6jdpnkpcer2picfbfu

Front Matter

2021 2021 IEEE Microelectronics Design & Test Symposium (MDTS)  
This year's theme is Innovation in Microelectronics for AI, Security, and New Advances in Computing.  ...  The symposium provides a forum for discussions on the latest issues in the design and test of microelectronics, broadening our scope from previous years.  ...  Title: Low-Cost Encryption Core for Resource-Constrained Applications Abstract: Resource-constrained systems such as Internet-of-things based devices have become increasingly more common.  ... 
doi:10.1109/mdts52103.2021.9476087 fatcat:niu4nujwobcfxnki6xfjdf7x34

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures [article]

Yu-Ting Chen, Jason Cong, Zhenman Fang, Bingjun Xiao, Peipei Zhou
2016 arXiv   pre-print
Third, to quickly develop applications that run seamlessly on the ARA prototype, ARAPrototyper provides a system software stack, abstracts the accelerators as software libraries, and provides APIs for  ...  In this paper we design and implement the ARAPrototyper to enable rapid design space explorations for ARAs in real silicons and reduce the tedious prototyping efforts far down to manageable efforts.  ...  For users to quickly develop their applications that use those accelerators, we abstract accelerators as software libraries and provide userfriendly C/C++ APIs to manipulate accelerators.  ... 
arXiv:1610.09761v1 fatcat:vc36crhlprfyroau2vgasubbtq
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