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FPGA based accelerator for visual features detection

Francois Brenot, Philippe Fillatreau, Jonathan Piat
2015 2015 IEEE International Workshop of Electronics, Control, Measurement, Signals and their Application to Mechatronics (ECMSM)  
in the Xilinx Zynq FPGA) to comply with the real-time constraints.  ...  DESIGN FLOW -EMBEDDED SLAM ARCHITECTURE Our works aim at embedding a vision-based EKF-SLAM process in a real-time system, in the context of an ADAS.  ... 
doi:10.1109/ecmsm.2015.7208697 fatcat:hekgnsdkgbh57gmdjwbwlapzzm

Real-time FPGA-based Visual Feature Extraction using FAST and BRIEF Algorithms

A. Al-Marakeby
2021 IJARCCE  
Fig.12 FPGA-based implementation of real time feature extraction  ...  Real-time implementation of visual feature extraction suffers from long latency, and heavy computation.  ...  Fig. 4 illustrates the proposed FPGAbased architecture for real-time implementation of FAST detector and BREIF descriptor.  ... 
doi:10.17148/ijarcce.2021.10401 fatcat:yte3j3prvzd7njaehr5255lvea

Author index

2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
- eration on FPGAs 0/1 Knapsack on Hardware: A Complete Solution A Compact Fading Channel Simulator Us- ing Timing-Driven Resource Sharing Hardware Design of a Binary Integer Deci- mal-based IEEE  ...  Support Framework for Linux Real-time FPGA-implementation for blue- sky Detection Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis Parallelizing HMMER for hardware accel  ... 
doi:10.1109/asap.2007.4459300 fatcat:lbxlom2lkrf2jf3q5c56uwiuea

High Level Synthesis Of Canny Edge Detection Algorithm On Zynq Platform

Hanaa M. Abdelgawad, Mona Safar, Ayman M. Wahba
2015 Zenodo  
Real time image and video processing is a demand in many computer vision applications, e.g. video surveillance, traffic management and medical imaging.  ...  The resulting implementation enables up to a 100x performance improvement through hardware acceleration.  ...  The implementation of stream-based Canny edge detector processing using C-based HLS is presented.  ... 
doi:10.5281/zenodo.1337955 fatcat:lwzpkbknozgobcpwkzgxvcnbs4

Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector

Sanjay Singh, Sumeet Saurav, Ravi Saini, Anil Kumar Saini, Chandra Shekhar, Anil Vohra
2014 ISRN Electronics  
This paper presents a comprehensive review and a comparative study of various hardware/FPGA implementations of Sobel edge detector and explored different architectures for Sobel gradient computation unit  ...  How the different architectures affected performance (in terms of video frame rate and image size) and area (in terms of FPGA resources usages) has been demonstrated.  ...  Acknowledgments This work was carried out under a project supported by Department of Electronics & Information Technology (DeitY), Ministry of Communications and Information Technology (MCIT), Government  ... 
doi:10.1155/2014/857912 fatcat:3kr2iar7evfszp2juu2pw236bm

FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application

Jia Wei Tang, Nasir Shaikh-Husin, Usman Ullah Sheikh, M. N. Marsono
2016 International Journal of Reconfigurable Computing  
The complex detection algorithm can be implemented in a real-time embedded system using Field Programmable Gate Array (FPGA).  ...  This paper presents the development of real-time moving target detection System-on-Chip (SoC) using FPGA for deployment on a UAV.  ...  Acknowledgments The authors would like to express their gratitude to Universiti Teknologi Malaysia (UTM) and the Ministry of Science, Technology and Innovation (MOSTI), Malaysia, for supporting this research  ... 
doi:10.1155/2016/8457908 fatcat:qjqprw4y4rhjbfo56bkhcrwiru

A hardware architecture of Prewitt edge detection

Aramesh Seif, Mohammad Mohammadpour Salut, Muhammad Nadzir Marsono
2010 2010 IEEE Conference on Sustainable Utilization and Development in Engineering and Technology  
Verilog hardware description language was used as the hardware programming language for a real-time edge detection system.  ...  The objective of this project is to develop a real-time hardware architecture for Prewitt edge detection algorithm. Prewitt edge detection provides differencing operation in the single kernel.  ...  [13] presents a real time implementation of two mathematical operators which are commonly used to detect edges.  ... 
doi:10.1109/student.2010.5686999 fatcat:nt5fzegsrbee7ajqpsdfcghrne

Real-time processing for Fourier domain optical coherence tomography using a field programmable gate array

Teoman E. Ustun, Nicusor V. Iftimia, R. Daniel Ferguson, Daniel X. Hammer
2008 Review of Scientific Instruments  
We have designed and developed an image processing system, including hardware based upon a field programmable gated array, firmware, and software that enables real-time display of processed images at rapid  ...  Real-time display of processed Fourier domain optical coherence tomography ͑FDOCT͒ images is important for applications that require instant feedback of image information, for example, systems developed  ...  FIG. 1 . 1 ͑ Schematic and ͑b͒ photograph of the real-time spectrometerbased FDOCT DSP hardware. ͑c͒ Schematic of the real-time swept source-based FDOCT DSP hardware.  ... 
doi:10.1063/1.3005996 pmid:19045902 pmcid:PMC2678783 fatcat:7pfkwqnggvbvlj2ukcywqdsb4i

Real-time implementation of foreground object detection from a moving camera using the ViBe algorithm

Tomasz Kryjak, Mateusz Komorkiewicz, Marek Gorgon
2014 Computer Science and Information Systems  
The article presents a real-time hardware implementation of a foreground object detection for a non-static camera setup.  ...  It allows to process a 720 × 576 pixels and 50 frames per second video stream in real-time.  ...  This work was supported by the AGH University of Science and Technology grants no. (first author), (second author) and (third author).  ... 
doi:10.2298/csis131218055k fatcat:ykregmhemvcjvliq25vv6h5bt4

Automatic license plate recognition on microprocessors and custom computing platforms: A review

Princewill Akpojotor, Adebayo Adetunmbi, Boniface Alese, Ayodeji Oluwatope
2021 IET Image Processing  
Drawbacks such as portability, power consumption and computational speed limit software-based ALPR for real-time deployment.  ...  ALPR systems could be realized on microprocessors (software-based) or custom computing platforms (hardware-based).  ...  ACKNOWLEDGEMENTS The authors would like to thank Science and Technology Education at the Post-Basic Level (STEP-B) for providing access to materials, through a World Bank grant for the establishment of  ... 
doi:10.1049/ipr2.12262 fatcat:wvlkalpj2na25aletvg377ww24

Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation

Hao XIAO, Yanming FAN, Fen GE, Zhang ZHANG, Xin CHENG
2020 IEICE transactions on information and systems  
Then, we further present an FPGA implementation of the proposed algorithm with an optimized real-time performance and resource efficiency.  ...  Thus, to fast and accurately extract the edge of the celestial body from high-resolution satellite imageries, this paper presents an algorithm-hardware co-design of real-time edge detection for OPNAV.  ...  Acknowledgments This work is supported in part by National Natural Science Foundation of China 61974039, 61834006, 61504059, 61674049, U19A2053, the Aeronautical Science Foundation of China 2018ZCP4, the  ... 
doi:10.1587/transinf.2020pcp0002 fatcat:c3bq7mhdkjg2rl6niovhvfdb7y

Reconfigurable architectures for parallel execution of image processing tasks

M. Gorgoń
2007 Opto-Electronics Review  
In the present paper, a new definition of parallelism adequate for fine-grain parallel systems is introduced. Computing power requirements for high definition, real-time vision system are discussed.  ...  A survey of reconfigurable solutions for image processing and the latest research work carried on at the AGH Laboratory of Biocybernetics are presented.  ...  Acknowledgements This work was supported in part by the Ministry of Science and Higher Education, as a research Project No. 4T11C01725.  ... 
doi:10.2478/s11772-007-0019-3 fatcat:hthjng5jnza6lmd2r22opk2dd4

Real-time background generation and foreground object segmentation for high-definition colour video stream in FPGA device

Tomasz Kryjak, Mateusz Komorkiewicz, Marek Gorgon
2012 Journal of Real-Time Image Processing  
The processing of a high-definition video stream in real-time is a challenging task for embedded systems.  ...  Finally, the complete system is implemented in a single high-end FPGA device.  ...  Acknowledgments The work presented in this paper was supported by the National Science Centre of the Republic of Poland under grant no. 2011/01/N/ST7/06687 (the first author) and Ministry of Science and  ... 
doi:10.1007/s11554-012-0290-5 fatcat:2c22a6zjnngebii6zz4pg7s2fa

Ground Control Point Automatic Extraction for Spaceborne Georeferencing Based on FPGA

Dequan LIU, Guoqing Zhou, Dianjun Zhang, Xiang ZHOU, Chenyang Li
2020 IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing  
The proposed system achieves 380 frame per second (fps) with a 100 MHz clock frequency, which satisfies the real-time and low-power requirements of embedded devices.  ...  The parallelization SURF detector, BRIEF descriptor, and BRIEF matching are implemented in a single Xilinx XC7VX980T FPGA system.  ...  [49] presented an efficient real-time FPGA implementation for object detection.  ... 
doi:10.1109/jstars.2020.2998838 fatcat:hgtwervnvrdwzhjbq4ytfmmniu

A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform

Florian Eibensteiner, Juergen Kogler, Josef Scharinger
2014 2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops  
To handle these and the correspondence problem in real time, we implemented our stereo matching algorithm for a field programmable gate array (FPGA).  ...  The results show that our matching criterion, based on the time of occurrence of an event, leads to a small average distance error and the parallel hardware architecture and efficient memory utilization  ...  In our work we present an approach implementing the stereo matching algorithm in hardware, such as FPGA platforms, facilitating a real-time computation of depth maps based on event-driven silicon retina  ... 
doi:10.1109/cvprw.2014.97 dblp:conf/cvpr/EibensteinerKS14 fatcat:vyb2lyjss5a5bnz37hstd6vu4i
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