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FPGA implementation of a minutiae extraction fingerprint algorithm

Mariano Lopez, Enrique Canto
2008 2008 IEEE International Symposium on Industrial Electronics  
This paper presents the implementation of a whole minutiae extraction fingerprint algorithm using a Spartan-3 FPGA, as an appropriate solution for portable devices and for the low-cost consumer market.  ...  The internal architecture of the proposed embedded system is based on a soft-core microprocessor and several dedicated coprocessors designed in order to accelerate the resolution of the algorithm.  ...  This paper presents a hardware-software co-design of a whole fingerprint algorithm implemented in a Xilinx low-cost Spartan 3 FPGA.  ... 
doi:10.1109/isie.2008.4676920 fatcat:obn3dbiuifbdzbbx6di6lnpp5e

Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware

M. Fons, F. Fons, E. Canto
2010 IEEE Transactions on Circuits and Systems - II - Express Briefs  
To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable  ...  The proposed system, which is implemented by means of hardware-software co-design techniques under a Virtex4 XC4VLX25 FPGA working at 100 MHz, is able to overcome in one order of magnitude the execution  ...  It deals with a hybrid fingerprint-matching algorithm that relies on the field orientation map and the set of minutia points extracted from the fingerprint impressions [9] .  ... 
doi:10.1109/tcsii.2010.2087970 fatcat:ono2r6syerdzzggfnnsmbw3z6e

Hardware-Software Codesign of a Fingerprint Identification Algorithm [chapter]

Nicolau Canyellas, Enrique Cantó, Giuseppe Forte, Mariano López
2005 Lecture Notes in Computer Science  
In this article we present a hardware/software implementation of a fingerprint minutiae extraction algorithm.  ...  The proposed system consists of a microprocessor and a coprocessor implemented in an associated FPGA.  ...  The algorithm is based on the idea of tracking the fingerprint ridge lines on the gray scale image by "sailing" over these points, according to the fingerprint directional image.  ... 
doi:10.1007/11527923_71 fatcat:oyjlaurpt5cb5jktr7mvsrksda

Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications [chapter]

Francisco Fons, Mariano Fons
2011 Recent Application in Biometrics  
Physical implementation of one computational platform based on a general-purpose MPU (system CPU), several hardware cores (HW coprocessors) and one memory block.  ...  A hybrid fingerprint matching algorithm that relies on the field orientation map and the set of minutia points extracted from the fingerprints is proposed for its physical implementation.  ...  Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications, Recent Application in Biometrics, Dr.  ... 
doi:10.5772/21500 fatcat:bxmridfkd5bkfif3ffnfmmnazi

Hardware–software co-design of an iris recognition algorithm

M. López, J. Daugman, E. Cantó
2011 IET Information Security  
This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design.  ...  The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application.  ...  That architecture, implemented on a Virtex II FPGA, is composed of a general purpose fixed-point processor and a DFT (Discrete Fourier Transform) hardware accelerator used to determine the dominant ridge  ... 
doi:10.1049/iet-ifs.2009.0267 fatcat:efsfr2envzfc3nxmmr24aj2kha

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López
2011 Journal of Real-Time Image Processing  
In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region  ...  algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative  ...  Biometric hardware coprocessors In our approach, most of the fingerprint image processing tasks described in Sect. 5 are implemented in the PRR of the FPGA as hardware coprocessors.  ... 
doi:10.1007/s11554-010-0186-1 fatcat:j5by7g5vpbfv3egkmqd6mzwhnq

An Efficient Reconfigurable Architecture for Fingerprint Recognition

Satish S. Bhairannawar, K. B. Raja, K. R. Venugopal
2016 VLSI design (Print)  
The proposed fusion based VLSI architecture is synthesized on Virtex xc5vlx30T-3 FPGA board using Finite State Machine resulting in optimized parameters.  ...  The novel matching score of CLBP is computed using histogram CLBP features of test image and fingerprint images in the database.  ...  The efficient FPGA architectures [17] [18] [19] [20] for fingerprint processing and existing algorithms to identify a fingerprint based on minutiae [21] , ridge, multiresolution features, and Hough  ... 
doi:10.1155/2016/9532762 fatcat:nkiwiu3u6vcujlsgu7bauttvq4


Dr. Nandhagopal N
2021 Zenodo  
., 2011], the IDO based algorithm was used for FPGA implementation, but we found the IDO less suitable compared to CHT for FPGA-based parallel implementation.  ...  The optional approach used to implement the iris detection algorithm was relied on a co-design of hardware software.  ... 
doi:10.5281/zenodo.5148811 fatcat:4pzov2mwtzd2hbgqsxib46snae