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FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

D. Pnevmatikatos, T. Becker, A. Brokalakis, K. Bruneel, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, M. Robart, M.D. Santambrogio (+3 others)
2012 2012 15th Euromicro Conference on Digital System Design  
The FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms  ...  with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology.  ...  Our contributions will span the analysis phase and the reconfigurable system definition, the support for multi-grain reconfiguration, the improved verification for the changing system, and the efficient  ... 
doi:10.1109/dsd.2012.59 dblp:conf/dsd/PnevmatikatosBBBGLPPPPRSSST12 fatcat:etaunro6tfcw3oi6ml3ifidhf4

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. Böhm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu (+9 others)
2015 Microprocessors and microsystems  
The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems.  ...  FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose  ...  Acknowledgement This work was supported by the European Commission -Belgium in the context of FP7 FASTER project (#287804).  ... 
doi:10.1016/j.micpro.2014.09.006 fatcat:35jcur7nljhw7hqletmdrqjhum

FASTER run-time reconfiguration management

Cătălin Bogdan Ciobanu, Dionisios N. Pnevmatikatos, Kyprianos D. Papadimitriou, Georgi N. Gaydadjiev
2013 Proceedings of the 27th international ACM conference on International conference on supercomputing - ICS '13  
Up to 4Gbps for DMA transfers, and up to 3Gbps for FPGA reconfiguration on Xilinx Virtex-5/6 devices is achieved.  ...  The FASTER project Run-Time System Manager offloads programmers from low-level operations by performing task placement, scheduling, and dynamic FPGA reconfiguration.  ...  Acknowledgments This work was supported by the European Commission in the context of FP7 FASTER project (#287804).  ... 
doi:10.1145/2464996.2467283 dblp:conf/ics/CiobanuPPG13 fatcat:pzlky5ilfjalliwham3w6ykkde

The FASTER vision for designing dynamically reconfigurable systems

M. D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt, D. Sciuto
2013 Proceedings of 2013 International Conference on IC Design & Technology (ICICDT)  
The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification  ...  The FASTER project will facilitate the use of reconfigurable hardware by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose  ...  ACKNOWLEDGMENT This work was supported by the European Commission in the context of FP7 FASTER project (#287804).  ... 
doi:10.1109/icicdt.2013.6563290 dblp:conf/icicdt/SantambrogioPPP13 fatcat:dzet3d5d7rbw7l7n23o73o53qe

Smart technologies for effective reconfiguration: The FASTER approach

M. D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga (+2 others)
2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification  ...  The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification  ...  The FASTER project (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) [1] aims at introducing a complete methodology to allow designers to easily implement and verify a system  ... 
doi:10.1109/recosoc.2012.6322881 dblp:conf/recosoc/SantambrogioPPPGSDBTLBCDS12 fatcat:eplvqvzqmfdirggcfr4qb53neq

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board

F. Spada, A. Scolari, G.C. Durelli, R. Cattaneo, M.D. Santambrogio, D. Sciuto, D.N. Pnevmatikatos, G.N. Gaydadjiev, O. Pell, A. Brokalakis, W. Luk, D. Stroobandt (+1 others)
2014 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications  
Even though FPGAs are becoming more and more popular as they are used in many different scenarios like communications and HPC, the steep learning curve needed to work with this technology is still the  ...  The paper discusses the steps done for the realization of the prototype and the results obtained on the target device.  ...  ACKNOWLEDGMENTS This work was partially funded by the European Commission in the context of the FP7 FASTER project (#287804).  ... 
doi:10.1109/ispa.2014.26 dblp:conf/ispa/SpadaSDCSSPGPBLSP14 fatcat:wqq4gfpomvf2jdfqoeqb55ot6a

Cheaper faster drug development validated by the repositioning of drugs against neglected tropical diseases

K. Williams, E. Bilsland, A. Sparkes, W. Aubrey, M. Young, L. N. Soldatova, K. De Grave, J. Ramon, M. de Clare, W. Sirawaraporn, S. G. Oliver, R. D. King
2015 Journal of the Royal Society Interface  
There is an urgent need to make drug discovery cheaper and faster.  ...  This will enable the development of treatments for diseases currently neglected for economic reasons, such as tropical and orphan diseases, and generally increase the supply of new drugs.  ...  We would like to thank Mehedi Nahian for help in the conversion of the experimental data to R.D.F.  ... 
doi:10.1098/rsif.2014.1289 pmid:25652463 pmcid:PMC4345494 fatcat:cy6lxgs6inc6bkrexkcpfux33e

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration

K. Papadimitriou, C. Pilato, D. Pnevmatikatos, M.D. Santambrogio, C. Ciobanu, T. Todman, T. Becker, T. Davidson, X. Niu, G. Gaydadjiev, W. Luk, D. Stroobandt
2012 2012 IEEE 15th International Conference on Computational Science and Engineering  
The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a design methodology and a tool flow that will enable designers to implement effectively  ...  and easily a system specification on a platform combining software and reconfigurable resources.  ...  ACKNOWLEDGMENT This work was supported by the European Commission in the context of FP7 FASTER project (#287804).  ... 
doi:10.1109/iccse.2012.61 dblp:conf/cse/PapadimitriouPPSCTBDNGLS12 fatcat:srjpj27qnvfx3j2mej2gnfgn4e

Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors

Siew-Kei Lam, Thambipillai Srikanthan
2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
In this paper, we propose a method to rapidly estimate the FPGA area costs of custom instructions without the need for hardware synthesis.  ...  FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures.  ...  This drives the need for technological advancement in both the computing platform and design process.  ... 
doi:10.1109/asap.2007.4429963 dblp:conf/asap/LamS07 fatcat:7zrufi5mbndvzkg43x4tmdebdy

Special Section Proposal Tunable Devices for Modern Communications: Materials, Integration, Modeling, and Applications

Andrei Muller, Richard W. Ziolkowski, Jusung Kim, Elena Blokhina, Mircea Dragoman, Maurizio Bozzi
2018 IEEE Access  
Onat, and the Publication Editors, Kimberly Shumard, Rebecca Hytowitz, and Margery Meyer for their help throughout the course of this Special Section.  ...  ACKNOWLEDGEMENTS We would like to thank all the authors and the reviewers for their efforts to make this Special Section successful. We would also like to thank the Editor-in-Chief, Prof.  ...  (co-authored by Richard Ziolkowski, Guest Editor of the Special Section), "Advances in reconfigurable antenna systems facilitated by innovative technologies," advances in reconfigurable antenna for future  ... 
doi:10.1109/access.2018.2855259 fatcat:m3otal33kjayfgdl5oxmdvq4gy

Low Power Reconfigurable Multiplier for Network on Chip Architecture

R. Sangeetha, T. Thangam
2019 International Journal of Software & Hardware Research in Engineering  
Approximate computing is promising system for low power Integrated Circuit(IC) structure and which restores a possibly approximate result rather than absolutely accurate result and using only error tolerant  ...  This work proposes architecture for an approximate multiplier with reconfigurable approximate CLA adder, accuracy of which can be designed during runtime.  ...  PERFORMANCE ANALYSIS In this section, the results obtained from synthesis and simulation reports are presented.  ... 
doi:10.26821/ijshre.7.5.2019.7502 fatcat:6bivvrv2ancs3l5actfng2kklq

Application of Machine Learning in Electromagnetics: Mini-Review

Md. Samiul Islam Sagar, Hassna Ouassal, Asif I. Omi, Anna Wisniewska, Harikrishnan M. Jalajamony, Renny E. Fernandez, Praveen K. Sekhar
2021 Electronics  
It extensively discusses recent research progress in the development and use of intelligent algorithms for antenna design, synthesis and analysis, electromagnetic inverse scattering, synthetic aperture  ...  are aiming for a cost-effective solution without excessive time consumption.  ...  For instance, the usual synthesis mechanism utilizing a full-wave electromagnetic simulator is gradually being replaced by faster and more cost-effective ML algorithms.  ... 
doi:10.3390/electronics10222752 fatcat:n6jb47p67fh47oyqhxiwldtevi

Performance Evaluation of Hybrid Reconfigurable Computing Architecture over Symmetrical FPGA

Sunil Kr Singh
2012 International Journal of Embedded Systems and Applications  
The two main types of programmable logic devices, field-programmable gate arrays (FPGA) based on LUTs technology and complex programmable logic device (CPLD) based on PLAs technology.  ...  For last few decades, reconfigurable devices have been extensively used in digital systems.  ...  Logic synthesis targeting FPGAs has been research extensively and numerous technology mapping approaches for LUT based FPGAs have been developed.  ... 
doi:10.5121/ijesa.2012.2312 fatcat:ntyrmdbizza6pl3q546imtgytu

FPGA and ASIC convergence

C. Valderrama, L. Jojczyk, P. DaCunha Possa, J. Dondo Gazzano
2011 2011 VII Southern Conference on Programmable Logic (SPL)  
Through the analysis of design methodologies and strategies facing multi-core, reconfigurability and power consumption challenges, this educational survey will follow that evolution approaching ASIC and  ...  The growing demands on multimedia applications and high-speed high-quality telecommunication systems with real-time constrains oriented to portable, low power consumption, devices, have being driven technologies  ...  In fact, continuous IC technology scaling facilitates the emergence of SoC and the access to reconfigurable hardware.  ... 
doi:10.1109/spl.2011.5782660 fatcat:tuym2sakgbhyxmkwjbj6tzfaqq

Proposal and analysis of a reconfigurable pulse shaping technique based on multi-arm optical differentiators

Mohammad H. Asghari, José Azaña
2008 Optics Communications  
The effective bandwidth of the output waveform is not necessarily limited by the input pulse bandwidth but rather it depends on the highest derivative order used for the pulse synthesis.  ...  technologies.  ...  This should facilitate the practical realization of the proposed technique; for instance, as other practical alternatives, the reconfigurable amplitude-only relative weights could be implemented using  ... 
doi:10.1016/j.optcom.2008.05.037 fatcat:ju2xl5s53rf35ewbcgfmu22oju
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