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FADE: A programmable filtering accelerator for instruction-grain monitoring

Sotiria Fytraki, Evangelos Vlachos, Onur Kocberber, Babak Falsafi, Boris Grot
2014 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)  
Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools.  ...  As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring.  ...  Sotiria Fytraki † , Evangelos Vlachos ‡ , Onur Kocberber † , Babak Falsafi † , Boris Grot * ‡ Oracle Labs † EcoCloud, EPFL * University of Edinburgh FADE: A Programmable Filtering Accelerator for Instruction-Grain  ... 
doi:10.1109/hpca.2014.6835922 dblp:conf/hpca/FytrakiVKFG14 fatcat:nc4v4tuuefftvo3ji4miiuymeu

Application-Specific Accelerators for Communications [chapter]

Yang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro
2010 Handbook of Signal Processing Systems  
However, not all DSP algorithms are appropriate for off-loading to a hardware accelerator.  ...  The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power.  ...  As such the need for acceleration at both the fine grain and coarse grain levels is often required, the former for instruction set architecture (ISA) like optimization and the latter for task like optimization  ... 
doi:10.1007/978-1-4419-6345-1_13 fatcat:bgppdcjc5zafdd4q2bwinepy2a

Application-Specific Accelerators for Communications [chapter]

Yang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro
2013 Handbook of Signal Processing Systems  
However, not all DSP algorithms are appropriate for off-loading to a hardware accelerator.  ...  The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power.  ...  As such the need for acceleration at both the fine grain and coarse grain levels is often required, the former for instruction set architecture (ISA) like optimization and the latter for task like optimization  ... 
doi:10.1007/978-1-4614-6859-2_23 fatcat:totrkiocljf4ni72xbsgboybdm

An experimental study of coarse-grained reconfigurable system-on-chip-based software-defined radio

Janakiraman NITHIYANANTHAM, Nirmal Kumar PALANISAMY
2016 Turkish Journal of Electrical Engineering and Computer Sciences  
Then a bandpass Chebyshev filter of 9.4 MHz with a ripple factor of 1 is used to maintain the conditions of orthogonality in the subcarriers.  ...  This paper describes the coarse-grained reconfigurable array (CGRA) implementations of SDR architecture.  ...  Acknowledgments This work was supported in part by the All India Council for Technical Education -Quality Improvement Programme Scheme 2010.  ... 
doi:10.3906/elk-1307-129 fatcat:kpjzuhz3wzgqbk33opkjbckr44

Run-time monitoring with adjustable overhead using dataflow-guided filtering

Daniel Lo, Tao Chen, Mohamed Ismail, G. Edward Suh
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
However, these run-time monitors can introduce large performance and energy overheads, especially for flexible systems that support a range of monitors.  ...  This allows a trade-off to be made between monitoring coverage and overhead.  ...  More recently, FADE [15] has been proposed as a general hardware module to perform this null metadata filtering for a variety of monitoring schemes.  ... 
doi:10.1109/hpca.2015.7056071 dblp:conf/hpca/LoCIS15 fatcat:4pels4gt6zdpvlddaudvqqee4y

PHMon: A Programmable Hardware Monitor and Its Security Use Cases

Leila Delshadtehrani, Sadullah Canakci, Boyou Zhou, Schuyler Eldridge, Ajay Joshi, Manuel Egele
2020 USENIX Security Symposium  
In this paper, we propose a minimallyinvasive and efficient implementation of a Programmable Hardware Monitor (PHMon) with expressive monitoring rules and flexible fine-grained actions.  ...  hardware-accelerated debugger.  ...  CNS-1916393 and CCF-1533663 and a Google Faculty Research award.  ... 
dblp:conf/uss/DelshadtehraniC20 fatcat:msjv6wkmnjbynh4nzewmazpzuu

An IoT Hardware Platform Architecture for Monitoring Power Grid Systems based on Heterogeneous Multi-Sensors

Phuoc Duc Nguyen, Hieu Quang Vo, Linh Ngoc Le, SeokJin Eo, LokWon Kim
2020 Sensors  
With the development of the system, we aim to achieve a solution with low cost, high flexibility and efficiency, and ease of deployment for the monitoring of power grid systems.  ...  transform through field-programmable-gate-array (FPGA)-based programmable logics.  ...  It combines a processing system and Xilinx programmable logic into a single device.  ... 
doi:10.3390/s20216082 pmid:33114629 pmcid:PMC7663348 fatcat:ur6so6yrujckboh3jzfkx26j7y

Design and Implementation of a Baseband WCDMA Dual-Antenna Mobile Terminal

Jean-Franois Frigon, Ahmed M. Eltawil, Eugene Grayver, Alireza Tarighat, Hanli Zou
2007 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals.  ...  Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity.  ...  All of these systems integrate on a single chip: a specific hardware accelerator for the WCDMA baseband transceiver (some chips are also multimode and include GSM, GPRS EDGE, HSDPA, and GPS accelerators  ... 
doi:10.1109/tcsi.2006.887620 fatcat:lsuzwta6fnerfih2ypkoiggvbq

Episodic dust formation by HD 192641 (WR 137) - II

P. M. Williams, M. R. Kidger, K. A. van der Hucht, P. W. Morris, M. Tapia, M. Perinotto, L. Morbidelli, A. Fitzsimmons, D. M. Anthony, J. J. Caldwell, A. Alonso, V. Wild
2001 Monthly notices of the Royal Astronomical Society  
Observations of the size and velocity dispersion of clusters suggest that protostellar migration from their birthplace begins at very early times and is a potentially useful evolutionary indicator.  ...  We acknowledge a Cormack Vacation Research Scholarship to VW from the Royal Society of Edinburgh.  ...  Finally, we thank David Florkowski for sight of his radio observations of WR 137 prior to publication and Sergey Marchenko and Viktor Zubko for helpful comments.  ... 
doi:10.1046/j.1365-8711.2001.04284.x fatcat:d7v7ilx3yffwtiosdgkb5ttrpi

NFV Platform Design: A Survey [article]

Tianzhu Zhang
2020 arXiv   pre-print
We believe that our study gives a detailed guideline for network operators or service providers to choose the most appropriate NFV platform based on their respective requirements.  ...  Then we thoroughly explore the design space and elaborate the implementation choices each platform opts for.  ...  Priyanka Naik for her valuable feedback.  ... 
arXiv:2002.11059v2 fatcat:zgafnd6xmvdzngkukq6qicf3gu

Toward virtual biopsy through an all fiber optic ultrasonic miniaturized transducer: a proposal

A. Acquafresca, E. Biagi, L. Masotti, D. Menichelli
2003 IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control  
channels ........Frequency-selective fading channels ........Rayleigh channels ........Weibull fading channels ....Filters ........Active filters ............Band-pass filters ........Anisotropic ....  ...  circuits ............Field programmable analog arrays ............Programmable logic arrays ............Programmable logic devices ........Programmable logic arrays ........Programmable logic devices  ... 
doi:10.1109/tuffc.2003.1244749 fatcat:l3jre4etsvcqzfyz2jqggji3gy

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Joo-Young Kim, Jeong-Ho Woo, Hoi-Jun Yoo
2013 IEEE Journal of Solid-State Circuits  
The context-aware visual attention model is proposed to reduce the required computing power for HD object recognition based on enhanced attention accuracy.  ...  GFLOPS giga floating operations per second TLP task-level parallelism DRM dynamic resource management ROI region-of-interests CAVAM context-aware visual attention model SoC system-on-a-chip ILP instruction-level  ...  Machine Learning Engine The architecture of MLE is as shown in Fig. 8(a) and it is designed for accelerating CAVAM's Kaman filter operation and DRC's reinforcement learning algorithm with different processing  ... 
doi:10.1109/jssc.2012.2220651 fatcat:uh4ec3i64vdmjdev5sgck7iv2i

Orbitally modulated dust formation by the WC7+O5 colliding-wind binary WR 140

P. M. Williams, S. V. Marchenko, A. P. Marston, A. F. J. Moffat, W. P. Varricatt, S. M. Dougherty, M. R. Kidger, L. Morbidelli, M. Tapia
2009 Monthly notices of the Royal Astronomical Society  
A third persistent dust concentration to the east of the binary (the 'arm') was found to have a proper motion ~ 320 mas/y.  ...  Comparison of model dust images and the observations constrain the intervals when the WCR was producing sufficiently compressed wind for dust nucleation in the WCR, and suggests that the distribution of  ...  Assuming a bulk density s g = 2 g cm −3 for the grain material, the acceleration at r = 125 au would be about 33 km s −1 per day for a 10 Å grain and not much less, 30 km s −1 per day, for a 100 Å grain  ... 
doi:10.1111/j.1365-2966.2009.14664.x fatcat:6ifwnckyjzarzjbbgv7az5s7o4

Exploring manycore architectures for next-generation HPC systems through the MANGO approach

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragić, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella (+22 others)
2018 Microprocessors and microsystems  
Acknowledgements This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671668.  ...  hardware fabric used to emulate the fine-grained accelerator tiles envisioned in the MANGO architecture.  ...  In addition, load gather and store scatter, masked instructions as well as other kind of vector instructions, such as shuffle or sign extension operations, are provided to the C/C++ programmer through  ... 
doi:10.1016/j.micpro.2018.05.011 fatcat:gf4jczkxgzcpfdbgqygmwbkwfq

Architectural Support to Accelerate Fine-Grain Program Monitoring

Sotiria Fytraki
2014
FADE: A Programmable Fil- tering Accelerator for Instruction-Grain Monitoring". Chapter 2 Background Table 1 : 1 Eight cases of access interleavings.  ...  Summary This chapter introduced FADE, a Filtering Accelerator for Decoupled Event monitoring.  ... 
doi:10.5075/epfl-thesis-6257 fatcat:mkvqgcbs3zaqnhqd6p66fkhpky
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