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Scalable hardware monitors to protect network processors from data plane attacks

Kekai Hu, Harikrishnan Chandrikakutty, Russell Tessier, Tilman Wolf
2013 2013 IEEE Conference on Communications and Network Security (CNS)  
Such hardware monitors have been studied extensively for single processor cores, but network processors consist of dozens to hundreds of processors with highly dynamic workloads.  ...  One possible defense mechanism for these resourceconstrained network processors is the use of hardware monitoring systems that track the operations of each processor core.  ...  Monitoring graph information is encrypted when it is transferred onto the network processor via an external interface.  ... 
doi:10.1109/cns.2013.6682721 dblp:conf/cns/HuCTW13 fatcat:wsfgq4pnb5akjmkvu7lzcr6gd4

Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs

Kizheppatt Vipin, Shanker Shreejith, Suhaib A. Fahmy, Arvind Easwaran
2014 2014 IEEE International Conference on Cyber-Physical Systems, Networks, and Applications  
Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on  ...  a processor.  ...  Due to the inherent parallelism in hardware, multiple sensors can be processed simultaneously and the architecture is highly scalable without affecting data acquisition performance.  ... 
doi:10.1109/cpsna.2014.14 dblp:conf/cpsna/VipinSFE14 fatcat:yam4aw6hmnaifjjsne3eau4tei

Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric

Muhammad Mukaram Khan, Javier Navaridas Palma, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Lujan, John Viv Woods, Jose Miguel-Alonso, Steve B. Furber
2009 2009 Eighth International Symposium on Parallel and Distributed Computing  
The architecture of SpiNNaker, a parallel chip multiprocessor (CMP) system for neural network simulation, is in this class.  ...  Where most large CMP systems feature a sideband network to complete the boot process, SpiNNaker has a single homogeneous network interconnect for both application inter-processor communications and system  ...  Navaridas is supported by a doctoral grant of the UPV/EHU and by the Spanish Ministry of Education and Science (Grant TIN2007-68023-C02-02).  ... 
doi:10.1109/ispdc.2009.25 dblp:conf/ispdc/KhanNRJPLWMF09 fatcat:bx2ce5yagfbntmzx47s5dq3fdu

Scalable communications for a million-core neural processing architecture

Cameron Patterson, Jim Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve Furber
2012 Journal of Parallel and Distributed Computing  
The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets  ...  The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software.  ...  Operation Neural-network simulation is a highly parallel task; each core is loaded with neural processing software and its neurons' local synaptic weights.  ... 
doi:10.1016/j.jpdc.2012.01.016 fatcat:szz343lkvvb4rcpvfek4oof2fa


Herbert B. Baskin, Barry R. Borgerson, Roger Roberts
1971 Proceedings of the November 16-18, 1971, fall joint computer conference on - AFIPS '71 (Fall)  
ACKNOWLEDGMENTS The authors wish to acknowledge the contributions of a number of people who include Larry Barnes, Robert Fabry, Domenico Ferrari, Richard Freitas, Charles Grant, Mar, Greenberg, Paul Morton  ...  The External Access Network treats all of the processor ports in a symmetrical manner.  ...  Each processor in the system can simultaneously connect to any two of the disk drives through the External Access Network as shown in Figure 2 .  ... 
doi:10.1145/1478873.1478929 dblp:conf/afips/BaskinBR72 fatcat:s4j5dsaad5ei7f3mga6ddemdfy

A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System

Zhen Zhang, Cheng Ma, Rong Zhu
2017 Sensors  
A single processor is not suitable for simulating highly interconnected networks, which will cause interprocessor messaging explosions [17] .  ...  A single processor is not suitable for simulating highly interconnected networks, which will cause interprocessor messaging explosions [17]. (a) (b)  ...  Table 1 . 1 Comparison of neuromorphic processors and General Purpose Processors (GPPs) for implementing neural network.  ... 
doi:10.3390/s17091941 pmid:28832522 pmcid:PMC5620544 fatcat:qgle6m2vybfjji52rgafwlanwy

SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor [chapter]

Stephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter Lee
2002 Lecture Notes in Computer Science  
TOTEM is digital VLSI parallel processor ideally suitable for vectormatrix multiplication.  ...  As such, it provides the core computational engine for digital signal processing and artificial neural network algorithms.  ...  Larger networks can be constructed by paralleling 2 to 16 chips, for a maximum network width of 255 neurons.  ... 
doi:10.1007/3-540-46117-5_113 fatcat:weticpntxjeuplxye5hshqphlu

Parallel Image Processing Using Algorithmic Skeletons

Sare Eslami Khorami
2014 International Journal of Intelligent Information Systems  
The present paper aims to present a technique for image processing which utilizes design and analysis of parallel algorithms.  ...  It employs a new approach called "algorithmic skeletons" which is composed of a set of programming templates; hence facilitating the programmers' work.  ...  Skeleton library Each skeleton can be executed on a set of processors. From this set of processors, a host processor is selected to split and distribute the image to the other processors.  ... 
doi:10.11648/j.ijiis.s.2014030601.12 fatcat:u6jihghwjvbmlb6znoidss775i

Implementatioin of Enhanced Transitional Communication Interface Between Mediums Using Adaptive Techniques

N L Sujatha Chavakula, A. Pravin, S. Kanaka Durga, G. Mallikarjuna
Implementation of an innovative and interactive device which is having the capability of changing its own properties with dynamic nature is presented in this project.  ...  Due to random change of properties like water flow, density; framed data energy may changes. So, modulation schemes have to be changed dynamically depends up on flow and density of water.  ...  The controlling section of this system is of great interest. The transmitted data is with the processor and s data are stored in the processor memory and continuously monitored.  ... 
doi:10.24297/ijct.v11i9.3412 fatcat:utygqbmn7raa5fhlyun6rbnf7e

Embedded Web Server based Interactive data acquisition and Control System

Miss.Pulate S.V Miss.Pulate S.V
2013 IOSR Journal of Electronics and Communication Engineering  
Single chip IDACS method increses the processing speed of a system and also avoids the problem of poor real time and reliability.This system uses ARM9 Processor and RTLinux.  ...  The global system of interconnected computer networks is called as World Wide Web which uses the standard Internet Protocol Suite (TCP/IP) to aid billion of users worldwide and enables the user to interface  ...  all the required tasks in parallel and in small amounts of time.  ... 
doi:10.9790/2834-562933 fatcat:o5qm6utjqffmrcl3oq2hlfn47u

A GALS Infrastructure for a Massively Parallel Multiprocessor

Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang
2007 IEEE Design & Test of Computers  
of Manchester, and also by ARM and Silistix.  ...  Acknowledgments The Spinnaker project is supported by the Engineering and Physical Sciences Research Coun-cil, partly through the Advanced Processor Technologies Portfolio Partnership at the University  ...  In the quest to understand the dynamics of neural systems, the Spinnaker multiprocessor, based on a highly parallel configuration of small, powerefficient processors and a GALS approach to on-chip and  ... 
doi:10.1109/mdt.2007.149 fatcat:4qt4nnnsbjgnvcno7pfzwiotdy

Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation

Simon W. Moore, Paul J. Fox, Steven J.T. Marsh, A. Theodore Markettos, Alan Mujumdar
2012 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines  
This contrasts with many FPGA-based neural systems which are very focused on parallel computation, resulting in inefficient use of FPGA resources.  ...  Our design allows 64k neurons with 64M synapses per FPGA and is scalable to a large number of FPGAs.  ...  Each node might be a more conventional CPU and coherent memory system (à la RAMP [1] ), or an implementation of a highly parallel algorithm (e.g. neural network simulation).  ... 
doi:10.1109/fccm.2012.32 dblp:conf/fccm/MooreFMMM12 fatcat:k7pa5iycwzcbvcfj47vbybgtqu

Radiation Transmission-based Thickness Measurement Systems - Advancements, Innovations and New Technologies [chapter]

Mark E.
2010 Advances in Measurement Systems  
User and External System Interfacing The highly networked nature of the system architecture (Figure 2 .5) and the C-Frame Controllers provide a number of opportunities for interfacing and scalability  ...  Figure 2 .5 provides a hierarchical view of this form of highly networked system arrangement. An interesting advancement is the Dedicated Thickness Measurement Network (DTMNet).  ... 
doi:10.5772/8728 fatcat:cobrah5wxbbazfrb4cawqgqsg4

Visualizing parallel simulations in network computing environments

Christopher D. Carothers, Brad Topol, Richard M. Fujimoto, John T. Stasko, Vaidy Sunderam
1997 Proceedings of the 29th conference on Winter simulation - WSC '97  
Parallel discrete event simulation systems (PDES) are used to simulate large-scale applications such as modeling telecommunication networks, transportation grids, and battlefield scenarios.  ...  While a large amount of PDES research has focused on employing multiprocessors and multicomputers, the use of networks of workstations interconnected through Ethernet or ATM has evolved into a popular  ...  The processor advance time is defined as the amount of wall clock time needed to advance the sim- Visualizing Parallel Simulations in Network Computing Environments ulation a single unit of simulation  ... 
doi:10.1145/268437.268459 fatcat:kdour2gq75bs7aus6zj75cn2vi

Resource-Aware Scientific Computation on a Heterogeneous Cluster

J.D. Teresco, J. Faik, J.E. Flaherty
2005 Computing in science & engineering (Print)  
Two efforts aim to improve the efficiency of scientific computation on clusters through resource-aware dynamic load balancing.  ...  Acknowledgments The development of Drum  ...  Alternately, if Drum can get a measure of available bandwidth (such as when the Network Weather Service 18 is monitoring the cluster), it can use this data to determine network powers in place of the  ... 
doi:10.1109/mcse.2005.38 fatcat:uyx5ugdv4nehxalaashjvgb4xy
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