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A framework for embedded system specification under different models of computation in SystemC

F. Herrera, E. Villar
2006 Proceedings - Design Automation Conference  
This paper presents a heterogeneous specification methodology built on top of the standard SystemC kernel.  ...  A main and distinguishing contribution of the methodology is that the support is provided while maintaining the standard kernel of SystemC unchanged, by means of a set of specification rules and a heterogeneous  ...  In [2] , the SystemC kernel extension for the support of heterogeneity is proposed. Kernel extension means that a set of new C++ classes enhances the set already provided by the SystemC kernel.  ... 
doi:10.1109/dac.2006.229411 fatcat:ffwj3lkcxrdm5ljsaqd7j7fi4q

A framework for embedded system specification under different models of computation in SystemC

F. Herrera, E. Villar
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
This paper presents a heterogeneous specification methodology built on top of the standard SystemC kernel.  ...  A main and distinguishing contribution of the methodology is that the support is provided while maintaining the standard kernel of SystemC unchanged, by means of a set of specification rules and a heterogeneous  ...  In [2] , the SystemC kernel extension for the support of heterogeneity is proposed. Kernel extension means that a set of new C++ classes enhances the set already provided by the SystemC kernel.  ... 
doi:10.1145/1146909.1147140 dblp:conf/dac/HerreraV06 fatcat:xz3an3f6pndp5bvvzi2md4jwzq

Formal techniques for SystemC verification

Moshe Y. Vardi
2007 Proceedings - Design Automation Conference  
It is fair to see that the development of formal-verification techniques for SystemC models is at its infancy.  ...  The difficulty stems from both the object-oriented nature of SystemC, which is fundamental to its modeling philosophy, and its sophisticated event-driven simulation semantics.  ...  SystemC has been developed with heavy intermodule communication in mind. The semantics of SystemC combined the semantics of C++ with the simulation semantics of the kernel.  ... 
doi:10.1145/1278480.1278527 dblp:conf/dac/Vardi07 fatcat:pucrpnf2kngmrmmvi64rg65gki

Concurrent Specification of Embedded Systems: An Insight into the Flexibility vs Correctness Trade-Off [chapter]

F. Herrera, I. Ugarte
2012 Embedded Systems - Theory and Design Methodology  
This type of modelling is required for speeding up the simulation of complex systems in new design activities, such as Design Space Exploration (DSE).  ...  However, to check whether such a property is fulfilled for every case requires the provision of the means for considering the different execution paths enabled by the control statements of an initially  ...  Current OSCI implementation of the SystemC simulation kernel fulfils the SystemC semantics and enables fast scheduling decisions.  ... 
doi:10.5772/37476 fatcat:hpkrk7lxhzcyxmilycmbtzfadm

The system verification methodology for advanced TLM verification

Marcio F.S. Oliveira, Christoph Kuznik, Hoang M. Le, Daniel Große, Finn Haedicke, Wolfgang Mueller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
As such, we first present SystemC libraries for the support of verification features like functional coverage and constrained random stimulus generation.  ...  Finally, we demonstrate the application of our SVM by means of a testbench for a two wheel self-balancing electric vehicle.  ...  ACKNOWLEDGMENTS This work was partly funded by the German Ministry of Education and Research (BMBF) through the project SANITAS (01M3088), the DFG SFB 614, the ITEA2 projects VERDE (01S09012) and TIMMO  ... 
doi:10.1145/2380445.2380497 dblp:conf/codes/OliveiraKLGH0DEE12 fatcat:uvdfxsquevglppocuxu2ybk3pa

RTOS-aware refinement for TLM2.0-based HW/SW designs

Markus Becker, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Mueller, Graziano Pravadelli, Tao Xie
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device  ...  The effectiveness of the methodology has been evaluated in the design of two complex platforms.  ...  The ISS ports have been added to the SystemC library as an extension of standard sc in and sc out ports.  ... 
doi:10.1109/date.2010.5456965 dblp:conf/date/BeckerGF0PX10 fatcat:h4sc5aol6rahxdz3e4ra5t6g7y

A SYSTEMC language extension for high-level reconfiguration modelling

Andreas Raabe, Armin Felke
2008 2008 Forum on Specification, Verification and Design Languages  
Details on the underlying simulation engine are given, which allows safe disabling and re-enabling of all process types without altering the kernel.  ...  This paper presents a library for modelling reconfiguration in the leading high-level system description language SYSTEMC combining IP reuse and high-level modelling with reconfiguration.  ...  In [2] a modified SystemC kernel is presented that allows enabling and disabling of processes. It is even used for modelling and simulation of a reconfigurable system.  ... 
doi:10.1109/fdl.2008.4641421 dblp:conf/fdl/RaabeF08 fatcat:wmpuatqmi5hx3c4wy3wqr2j6ne

Verifying SystemC using an intermediate verification language and symbolic simulation

Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
2013 Proceedings of the 50th Annual Design Automation Conference on - DAC '13  
Formal verification of SystemC is challenging. Before dealing with symbolic inputs and the concurrency semantics, a front-end is required to translate the design to a formal model.  ...  The lack of such front-ends has hampered the development of efficient back-ends so far. In this paper, we propose an isolated approach by using an Intermediate Verification Language (IVL).  ...  To verify the abstract SystemC models, the straight-forward approach is simulation offered already by the free event-driven simulation kernel shipped with the SystemC class library [1] .  ... 
doi:10.1145/2463209.2488877 dblp:conf/dac/LeGHD13 fatcat:ppd3t355mzahrcw6sdkfu6677e

Towards analyzing functional coverage in SystemC TLM property checking

Hoang M. Le, Daniel Grose, Rolf Drechsler
2010 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
For Electronic System Level (ESL) design SystemC has become the standard language due to its excellent support of Transaction Level Modeling (TLM).  ...  We present a coverage approach which can analyze whether the property set unambiguously describes all transactions in a SystemC TLM model.  ...  SystemC has been implemented as a C++ class library, which includes an event-driven simulation kernel.  ... 
doi:10.1109/hldvt.2010.5496658 dblp:conf/hldvt/LeGD10 fatcat:bk4bcznaifcofhtzoxo3ye5heu

Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications

Chulho Shin, Peter Grun, Nizar Romdhane, Christopher Lennard, Gabor Madl, Sudeep Pasricha, Nikil Dutt, Mark Noll
2007 Design automation for embedded systems  
Not only is the RTL simulation speed too slow to allow adequate coverage of the large design space in modern SoC designs, but making small changes in the design can require considerable re-engineering  ...  For example, cycle-based scheduling is a concept in cycle-accurate modeling that can increase the simulation speed without losing clock-cycle accuracy of the system.  ...  kernel, we chose the OSCI SystemC simulator as an example of an event-driven simulation kernel, and ARM RealView SoC Designer with MaxSim technology as an example of a cycle-level simulation kernel.  ... 
doi:10.1007/s10617-007-9003-x fatcat:ewdww5lwnvc4tinvf5an2fy3ae

An AOP-Based Security Verification Environment for KECCAK Hash燗lgorithm

Hassen Mestiri, Imen Barraj, Mohsen Machhout
2022 Computers Materials & Continua  
concerns discuss the effect of the AOP on simulation time and executable file size.  ...  The current study presents a fault injection/detection environment for assessing the KECCAK SystemC model's resistance against fault injection attacks.  ...  The user time (uTime) and kernel time (kTime) simulations for the two situations are shown in Tab. 2.  ... 
doi:10.32604/cmc.2022.029794 fatcat:4fxcgaukr5d5vpu6agkiyswvli

Formal verification of probabilistic SystemC models with statistical model checking

Van Chan Ngo, Axel Legay
2017 Journal of Software: Evolution and Process  
Moreover, users can define their own fine-grained time resolution rather than the boundary of clock cycles in the SystemC simulation.  ...  The first contribution of this work is a framework to verify properties expressed in Bounded Linear Temporal Logic (BLTL) for SystemC models with both timed and probabilistic characteristics.  ...  These propositions help users exposing the state of the SystemC simulation kernel and the full state of the SystemC source code model.  ... 
doi:10.1002/smr.1890 fatcat:aebjwm7blncaxhgjfiwfs7bw74

Analogue mixed signal simulation using spice and SystemC

T. Kirchner, N. Bannow, C. Grimm
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
SystemC is a discrete event simulator that enables the programmer to model complex designs with varying levels of abstraction.  ...  In order to improve precision, it can be coupled to more specialized simulators. This article introduces the concept of loose simulator coupling between an analogue simulator and SystemC.  ...  Another attempt to extend SystemC simulation capabilities is SystemC AMS Extensions. It is an extension to the SystemC language that aims at analogue designs [3] , [4] . II.  ... 
doi:10.1109/date.2009.5090672 dblp:conf/date/KirchnerBG09 fatcat:kkmosdb64vf5nlkhw2girapyie

A Methodology for Modelling and Simulation of Dynamic and Partially Reconfigurable Systems [chapter]

Alisson Vasconcelos, George Silveira, Elmar Uwe Kurt Melcher
2010 Dynamic Modelling  
The scheduler is part of the simulator kernel, and decides the execution sequence for each cycle.  ...  linked lists added to SystemC simulator kernel.  ...  A Methodology for Modelling and Simulation of Dynamic and Partially Reconfigurable Systems, Dynamic Modelling, Alisson V.  ... 
doi:10.5772/7094 fatcat:n4vysj6rr5gwjeqatzayhrefdy

C-Based Design of Heterogeneous Embedded Systems

Christoph Grimm, Axel Jantsch, Sandeep Shukla, Eugenio Villar
2008 EURASIP Journal on Embedded Systems  
The first two articles offer a deeper insight into the problems and also potential solutions: the first paper "Power aware simulation framework for wireless sensor networks and nodes" by Glaser et al.  ...  a design technology that integrates all kind of components for the realization of future "ambient intelligence" systems.  ...  Approaches to improve verification coverage range from model-driven validation in the ninth article "Model-driven validation of SystemC designs" by Patel et al. to simulators that allow designers to integrate  ... 
doi:10.1155/2008/243890 fatcat:iwtnbjdnybgyhfm7vsswi6fxkm
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