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Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications

Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
To attack this mismatch, this paper proposes a multicore architecture, referred to as Voltron, that extends traditional multicore systems in two ways.  ...  However, for desktop and other systems where single-thread applications dominate, multicore systems have yet to offer much benefit.  ...  Much gratitude goes to the anonymous referees who provided helpful feedback on this work.  ... 
doi:10.1109/hpca.2007.346182 dblp:conf/hpca/ZhongLM07 fatcat:sauqiioqtvfaro65x6xyffqr6m

Design and Implementation of Hybrid and Native Communication Devices for Java HPC

Bibrak Qamar, Ansar Javed, Mohsan Jameel, Aamir Shafi, Bryan Carpenter
2014 Procedia Computer Science  
In the multicore mode, the parallel Java application executes on a single system comprising of shared memory or multicore processors.  ...  In this paper, we extend the MPJ Express software to provide two new communication devices namely the native and hybrid device.  ...  In the context of hybdev, we plan to investigate efficient collective communication algorithms that exploit locality of processes on clusters built with shared memory and multicore processors.  ... 
doi:10.1016/j.procs.2014.05.017 fatcat:7xsp2mcsbvcjlofked4kbuhf3u

Parallelism via Multithreaded and Multicore CPUs

A.C. Sodan, J. Machina, A. Deshmeh, K. Macnaughton, B. Esbaugh
2010 Computer  
The additional capacity was used in the past for development of superscalar CPUs with replicated execution units and deep pipelines to exploit instruction-level parallelism.  ...  Multithreaded and multicore designs support multitasking via parallel programs or running several applications concurrently.  ...  This article has been accepted for publication in Computer but has not yet been fully edited. Some content may change prior to final publication.  ... 
doi:10.1109/mc.2010.75 fatcat:z34ptnd3rbgdvf7md5dmmqinfm

A survey on hardware-aware and heterogeneous computing on multicore processors and accelerators

Rainer Buchty, Vincent Heuveline, Wolfgang Karl, Jan-Philipp Weiss
2011 Concurrency and Computation  
We outline architectural features and show, how these features are exposed to the programmer and how they can be beneficially utilized in the application-mapping process.  ...  In particular, we characterize the discrepancy to conventional parallel platforms with respect to hierarchical memory sub-systems, fine-grained parallelism on several system levels, and chip-and system-level  ...  Acknowledgements The Shared Research Group 16-1 received financial support by the Concept for the Future of Karlsruhe Institute of Technology in the framework of the German Excellence Initiative and the  ... 
doi:10.1002/cpe.1904 fatcat:fwg2vjaobral3b2v46vq4x2c3q

JEOPARD -- Java Environment for Parallel Real-Time Development

Fridtjof Siebert
2009 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing  
However, a more fundamental change in the design and development of software is required to fully exploit the power of multicore systems.  ...  The JEOPARD project addresses this demand by developing Java software tools to exploit multicore power while ensuring correctness and predictable timing.  ...  Contributions came from all project partners, in particular from Jose Almeida, Neil Audsley, Jacques Brygier, Annalisa Durantini, Scott Hansen, Thomas Mahr, Vlad Olaru, Ingo Prötel, Martin Schoeberl, Tobias  ... 
doi:10.1109/isorc.2009.48 dblp:conf/isorc/Siebert09 fatcat:fmm3wrfbgnbcrj3kejtpn67clm

JEOPARD

Fridtjof Siebert
2008 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems - JTRES '08  
However, a more fundamental change in the design and development of software is required to fully exploit the power of multicore systems.  ...  The JEOPARD project addresses this demand by developing Java software tools to exploit multicore power while ensuring correctness and predictable timing.  ...  Contributions came from all project partners, in particular from Jose Almeida, Neil Audsley, Jacques Brygier, Annalisa Durantini, Scott Hansen, Thomas Mahr, Vlad Olaru, Ingo Prötel, Martin Schoeberl, Tobias  ... 
doi:10.1145/1434790.1434804 dblp:conf/jtres/Siebert08 fatcat:uoiptzaodfdfneyb3ipxnqla5u

Exploiting Fine-Grain Thread Parallelism on Multicore Architectures

P.E. Hadjidoukas, G.Ch. Philos, V.V. Dimakopoulos
2009 Scientific Programming  
In this work we present a runtime threading system which provides an efficient substrate for fine-grain parallelism, suitable for deployment in multicore platforms.  ...  Its architecture encompasses a number of optimizations that make it particularly effective in managing a large number of threads and with low overheads.  ...  . / Exploiting fine-grain thread parallelism on multicore architectures Fig. 5.  ... 
doi:10.1155/2009/249651 fatcat:tjc25fxytnfgve5o2j5ijq22uy

Multicores in Cloud Computing: Research Challenges for Applications

Lizhe Wang, Jie Tao, Gregor Von Laszewski, Holger Marten
2010 Journal of Computers  
of multicore for high performance applications in the Cloud environments.  ...  However, to fully exploit the computational capacity and the other advantages of multicores, a lot of novel techniques must be proposed and investigated.  ...  THE MULTICORE ARCHITECTURE According to Moore's law, billions of transistors can be integrated on a single chip in the near future.  ... 
doi:10.4304/jcp.5.6.958-964 fatcat:w7uw2hf7analhadyn7nqrabvym

MHPM: Multi-Scale Hybrid Programming Model: A Flexible Parallelization Methodology

Nader Khammassi, Jean-Christophe Le Lann, Jean-Philippe Diguet, Alexandre Skrzyniarz
2012 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems  
The continuous proliferation of multicore architectures has placed a great pressure on developers to parallelize their applications accordingl y with what such platforms can offer .  ...  In this paper, we propose a flexible parallelization methodology, and we introduce a new task-based hybrid programming model (MHPM) designed to provide high productivity and expressiveness without sacrificing  ...  Exploiting software parallelism on these emerging heterogeneous multicore architectures has become a great design challenge which outline the need for new technologies to make multicore processors more  ... 
doi:10.1109/hpcc.2012.20 dblp:conf/hpcc/KhammassiLDS12 fatcat:iub7egxn2rcuhm72kl7qwopzbq

Techniques for Enabling Highly Efficient Message Passing on Many-Core Architectures

Min Si, Pavan Balaji, Yutaka Ishikawa
2015 2015 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing  
Many-core architecture provides a massively parallel environment with dozens of cores and hundreds of hardware threads.  ...  In the thesis, we investigate the characteristics of MPI on such massively threaded architectures and propose two efficient strategies-a multithreaded MPI approach and a process-based asynchronous model-to  ...  In the common mode of hybrid MPI+OpenMP applications, multiple threads are used to parallelize the computation, while one of the threads handles MPI communication (i.e., MPI FUNNELED or SERIALIZED threadsafety  ... 
doi:10.1109/ccgrid.2015.68 dblp:conf/ccgrid/SiBI15 fatcat:edzfgmxrhfhvxbohfatxdei5ly

An Application based Efficient Thread Level Parallelism Scheme on Heterogeneous Multicore Embedded System for Real Time Image Processing

K Indragandhi, Jawahar P K
2020 Scalable Computing : Practice and Experience  
In order to utilize all the core in multicore processor in an efficient manner, application programs need to be parallelized.  ...  An efficient thread level parallelism (ETLP) scheme is proposed in this paper and uses computationally intensive edge detection algorithm for evaluation.  ...  The main idea of proposed Efficient Thread Level Parallelism (ETLP) scheme is to exploit the full processing power of multicore processor by using parallel programming model for multithreaded application  ... 
doi:10.12694/scpe.v21i1.1611 fatcat:kztcelxhffcpvnilwixw76ce2e

Simulation of hybrid computer architectures: simulators, methodologies and recommendations

Pranav, Jaehwan John Lee
2007 2007 IFIP International Conference on Very Large Scale Integration  
It is essential to investigate the computer architecture of such hybrid computing machines that utilize reconfigurable logic coprocessors as application accelerators in a HPC system.  ...  Simulation can be used to aid this architectural research and guide design space exploration. In this paper, we first present a representative architecture for future hybrid computing machines.  ...  Furthermore, WWT II performs parallel simulation by exploiting the parallelism inherent in the target parallel computer to achieve speed-ups of up to 5.8X.  ... 
doi:10.1109/vlsisoc.2007.4402490 dblp:conf/vlsi/VaidyaL07 fatcat:kzamgosiyndxnec6lhos7pbmru

The Impact of Resource Sharing Control on the Design of Multicore Processors [chapter]

Chen Liu, Jean-Luc Gaudiot
2009 Lecture Notes in Computer Science  
exploitation of Thread-Level Parallelism (TLP) as well as ILP.  ...  Since Instructional-Level Parallelism (ILP) is inherently limited, one single thread is not capable of efficiently utilizing the resource of a single core.  ...  As such, attempting to exploit Thread-Level Parallelism (TLP) is an effort to overcome the limitation due to low ILP within a single program.  ... 
doi:10.1007/978-3-642-03095-6_31 fatcat:ksky4sfv6vcsnadx7hkngm3yi4

ProtTest 3: fast selection of best-fit models of protein evolution

Diego Darriba, Guillermo L. Taboada, Ramón Doallo, David Posada
2011 Computer applications in the biosciences : CABIOS  
., 2007) that can be executed in parallel in multi-core desktops and clusters. This version, called ProtTest 3, includes new features and extended capabilities.  ...  Availability-ProtTest 3 source code and binaries are freely available under GNU license for download from http://darwin.uvigo.es/software/prottest3, linked to a Mercurial repository at Bitbucket (https  ...  . (3) a hybrid implementation MPJ -OpenMP (Dagum and Menon, 1998) to obtain maximum scalability in architectures with both shared and distributed memory (e.g., multicore HPC clusters).  ... 
doi:10.1093/bioinformatics/btr088 pmid:21335321 pmcid:PMC5215816 fatcat:ire76bw2evbvbkr4zliqy64lsm

Multi-Threaded OpenSHMEM

Gabriele Jost, Ulf R. Hanebutte, James Dinan
2014 Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models - PGAS '14  
The purpose of this document is to stimulate discussions on support for multi-threaded execution in OpenSHMEM.  ...  In our ongoing work, we investigate opportunities and challenges introduced through multi-threading, namely implementation challenges and opportunities and requiredas well desirableextensions to the API  ...  Hybrid parallel programming with processes and threads is a popular remedy to this problem, because it extends existing process-based parallel programming libraries with intranode data sharing [3] .  ... 
doi:10.1145/2676870.2676890 dblp:conf/pgas/JostHD14 fatcat:5iasa3trxzebtbgllgtff2xeea
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