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RISC-V Based Safety System-on-Chip with Hardware Comparator [chapter]

Eike Hahn, Dominik Kalinowski, Waldemar Mueller, Mohamed Abdelawwad, Josef Boercsoek
2021 Frontiers in Artificial Intelligence and Applications  
In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed.  ...  The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.  ...  Ethernet Communication Figure 7. Hardware Comparator Structure E. Hahn et al. / RISC-V Based Safety System-on-Chip with Hardware Comparator  ... 
doi:10.3233/faia210423 fatcat:prdd6twjzna4nh5u3d6zjml7xq

A Survey on RISC-V Security: Hardware and Architecture [article]

Tao Lu
2021 arXiv   pre-print
This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Based on our survey, we predict the future research and development directions of RISC-V security.  ...  For decades, these processors were mainly based on the Arm instruction set architecture (ISA).  ...  Porting classic security applications of other architectures to RISC-V will be major and important tasks in the near future. For example, the RISC-V community is porting Arm's OP-TEE implementation.  ... 
arXiv:2107.04175v1 fatcat:hr6avyprj5dvpav2pvnmfmvg2a

The MareNostrum Experimental Exascale Platform (MEEP)

2021 Supercomputing Frontiers and Innovations  
Nascent Open Source Instruction Set Architectures such as OpenPOWER or RISC-V, allow software/hardware co-designers to fully utilize the underlying hardware, modify it or extend it based on their needs  ...  The RISC-V ecosystem is in the nascent period where it can become the de facto open hardware platform of the future, having the same opportunity in hardware that Linux created as a foundation for OSS.  ...  In addition to RISC-V architecture and hardware ecosystem improvements, MEEP also advances the RISC-V software ecosystem with an enhanced and extended software toolchain and software stack, including a  ... 
doi:10.14529/jsfi210105 fatcat:skh2whflyzhbdmgebvthb4rcru

Adaptation of DSP Processors for 3G and 4G Wireless Communication
English

VINNI SHARMA, TANUJA KASHYAP
2014 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering  
This paper illustrates the role of Digital Signal Processors for Third generation (3G) mobile systems and DSP architectures for 4G wireless communication.  ...  DSP Architectures for 3G Mobile Communications Systems: The choice of a DSP to obtain the required computation speed is not a direct matter of specifying the highest clock speed Architecture and instruction  ...  After that in section V we have discussed programmable digital signal processors for 3G mobile.  ... 
doi:10.15662/ijareeie.2014.0307041 fatcat:2xgq7v2aczfufhsizdju2llqsi

Mapping of MPEG-4 decoding on a flexible architecture platform

Erik B. van der Tol, Egbert G. Jaspers, Sethuraman Panchanathan, V. Michael Bove, Jr., Subramania I. Sudharsanan
2001 Media Processors 2002  
As a representative application, this paper presents the mapping of a Main Visual profile MPEG-4 for High-Definition (HD) video onto a flexible architecture platform.  ...  , and the reuse potential over different applications and different systems.  ...  ACKNOWLEDGMENTS The authors would like to thank Jos van Eijndhoven, Martijn Rutten, and Koen Meinds from Philips Research for their contribution and suggestions to this work.  ... 
doi:10.1117/12.451067 fatcat:gzzbtvu5q5gypjchdvdo27ofny

Conference Report From The 57th Design Automation Conference

Zhuo Li
2020 IEEE design & test  
: RISC-V, die to die communication IP, IP security. • Embedded systems: 5G system architectures, edge-based ML, and audio/voice technologies.  ...  RISC-V has ushered in a profound shift in the technical and business models for microprocessors. On Wednesday, Cerebras Systems Inc.  ... 
doi:10.1109/mdat.2020.3024151 fatcat:gv4j6wz5rbdd5jyfk2jcyph7hq

An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
This paper proposes a new architecture for a singlechip MPEG-2 video encoder with scalability for HDTV and demonstrates its exibility and usefulness.  ...  The architecture based on three-layer cooperation provides exible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality.  ...  Ryota Kasai of the NTT System Electronics Laboratories for supporting this work. Thanks are also due to the members of the NTT Visual Communication Laboratory for their helpful suggestions.  ... 
doi:10.1145/307418.307445 fatcat:nosqizpxprbizdqhvftfuuymmm

Research on Fault-Tolerant Control System for Space Modular Manipulator System

Ping YE, Han-xu SUN, Qing-xuan JIA, Xin-sheng WANG
2006 Chinese Journal of Aeronautics  
The features of the hardware and software of the fault-tolerant control system are presented. The performance specifications are also discussed.  ...  This paper studies a fault-tolerant control system for a space modular manipulator system mounted on space station or other spacecrafts such as satellites, located in low earth orbit.  ...  Thus, the high reliability of the FTCS is ensured by hardware Fig.1 Hardware architecture of the FTCS redundancy at system level.  ... 
doi:10.1016/s1000-9361(11)60354-3 fatcat:jzttzpmwofbklm3mqmux3eimpq

Digital Signal Processing Accelerator for RISC-V

L. Calicchia, V. Ciotoli, G. C. Cardarilli, L. di Nunzio, R. Fazzolari, A. Nannarelli, M. Re
2019 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)  
General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications  ...  that users recognise and abide by the legal requirements associated with these rights.  Users may download and print one copy of any publication from the public portal for the purpose of private study  ...  CONCLUSIONS AND FUTURE WORK In this paper we presented an accelerator for the RISC-V ecosystem, suitable for digital FIR filtering, bi-dimensional convolution and pattern matching.  ... 
doi:10.1109/icecs46596.2019.8964670 dblp:conf/icecsys/CalicchiaCCNFNR19 fatcat:3kcpht3l3bg2bgsjuidftiq75e

SRACARE: Secure Remote Attestation with Code Authentication and Resilience Engine [article]

Avani Dave, Nilanjan Banerjee, Chintan Patel
2021 arXiv   pre-print
The prototype employs an efficient lightweight, low-power 32-bit RISC-V processor, secure communication protocol, code authentication, and resilience engine running on the Artix 7 Field Programmable Gate  ...  However, the majority of them lack in providing onboard system recovery and secure communication techniques.  ...  RISC-V.  ... 
arXiv:2101.06148v1 fatcat:32nhxxm46ndy5pz4adqtfxg4lq

64 Bit Computer Architectures For Space Applications – A Study

Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy
2009 Zenodo  
They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher  ...  The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems  ...  TABLE I DETAILED I DESCRIPTION OF SIGNALS (RISC MICROPROCESSOR) Total estimated signal pins for 64 bit RISC Architecture = 368 pins Total estimated signal pins for 32 bit RISC Architecture = 272 pins The  ... 
doi:10.5281/zenodo.1061311 fatcat:g5fmbo3gxvepvhugpchzgzvthi

FPGA Implementation of On-Chip Network

N Murali Krishna
2018 DJ Journal of Advances in Electronics and Communication Engineering  
Coarse Grained Arrays (CGAs) with run-time re-configurability play a challenging task to design Network on-Chip (NoC) communication systems satisfying the power and area of embedded system.  ...  The proposed architecture is implemented on FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language), and the obtained comparison power graph signifies that it consumes less  ...  The advanced version of this processor and software paves way for the application in future embedded systems [9].  ... 
doi:10.18831/djece.org/2018021001 fatcat:jfgj5g733zbi5mgkfypfzvn6ga

Challenges and Opportunities for FPGA Platforms [chapter]

Ivo Bolsens
2002 Lecture Notes in Computer Science  
architects, hardware & software engineers, DSP & communications specialists PPC PPC Towards programmable platforms • 32-bit RISC CPU, Harvard Architecture • 130nm CMOS with 1.5V Operation •  ...  Logic• Built-In Hardware Timers • Built-In JTAG Debug and Trace support Xilinx "Low PowerPC": 0.59mW/MIPS System Architecture Options • "Logic-Centric Architecture" -PowerPC Executes Entirely out of Cache  ... 
doi:10.1007/3-540-46117-5_41 fatcat:eftclfmcgvbu3dualab7mf43ta

The TaPaSCo Open-Source Toolflow

Carsten Heinz, Jaco Hofmann, Jens Korinth, Lukas Sommer, Lukas Weber, Andreas Koch
2021 Journal of Signal Processing Systems  
This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip.  ...  A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study  ...  With regard to the system composition, a similar approach is used by the HERO framework for research in RISC-V-based manycore SoCs [44] .  ... 
doi:10.1007/s11265-021-01640-8 fatcat:t5y5t5vmp5ff3h635cx3y7to6e

Soft-Core Processors for Embedded Systems

Jason G. Tong, Ian D. L. Anderson, Mohammed A. S. Khalid
2006 2006 International Conference on Microelectronics  
Several soft-core processors available from commercial vendors and open-source communities are reviewed and compared based on major architectural features.  ...  A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target.  ...  We conclude in Section V with some comments on future work in the area of soft-core processors. II.  ... 
doi:10.1109/icm.2006.373294 fatcat:xlxvjjifvngzrm6bie34g2cw54
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