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Expression and Loop Libraries for High-Performance Code Synthesis [chapter]

Christopher Mueller, Andrew Lumsdaine
Languages and Compilers for Parallel Computing  
In this paper, we use the SPE to develop two code generation libraries, one for scalar and vector (SIMD) expression evaluation and another for parallel and high-performance loop generation.  ...  Our results show that scripting languages can be used to generate high-performance code and suggest that providing optimizations as user-level libraries is an effective strategy for managing the complexity  ...  The Iterator Library Variables and expressions provide the foundation for developing syntactically clear high-performance synthetic programs.  ... 
doi:10.1007/978-3-540-72521-3_7 dblp:conf/lcpc/MuellerL06 fatcat:v54wj7elgrcetgygz3fd4udcjq

Techniques for synthesizing binaries to an advanced register/memory structure

Greg Stitt, Zhi Guo, Walid Najjar, Frank Vahid
2005 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05  
Furthermore, we compare the binary results using smart buffers with results of synthesis directly from the original C code for the benchmarks, and show that our methods achieved almost identical performance  ...  However, recent synthesis methods for FPGAs utilize advanced memory structures, such as a "smart buffer," that require recovery of additional high-level information, specifically information about loops  ...  SUIF provides high-level information about loops and memory accesses, which ROCCC uses to perform loop level analysis and optimizations.  ... 
doi:10.1145/1046192.1046208 dblp:conf/fpga/StittGNV05 fatcat:sagxrajqtbdctlvd3vmxptyjxq

Towards Automatic Synthesis of High-Performance Codes for Electronic Structure Calculations: Data Locality Optimization [chapter]

D. Cociorva, J. Wilkins, G. Baumgartner, P. Sadayappan, J. Ramanujam, M. Nooijen, D. Bernholdt, R. Harrison
2001 Lecture Notes in Computer Science  
This paper provides an overview of a planned synthesis system that will take as input a high-level specification of the computation and generate high-performance parallel code for a number of target architectures  ...  The goal of our project is the development of a program synthesis system to facilitate the development of high-performance parallel programs for a class of computations encountered in computational chemistry  ...  Acknowledgments We would like to thank the Ohio Supercomputer Center (OSC) for the use of their computing facilities, and the National Science Foundation for partial support through grants DMR-9520319,  ... 
doi:10.1007/3-540-45307-5_21 fatcat:6gdgmt65gbb6dhxsgouuwxyyjm

A High-Level Approach to Synthesis of High-Performance Codes for Quantum Chemistry

G. Baumgartner, D.E. Bernholdt, D. Cociorva, R. Harrison, So Hirata, Chi-Chung Lam, M. Nooijen, R. Pitzer, J. Ramanujam, P. Sadayappan
2002 ACM/IEEE SC 2002 Conference (SC'02)  
This paper discusses an approach to the synthesis of high-performance parallel programs for a class of computations encountered in quantum chemistry and physics.  ...  An overview is provided of the synthesis system, that transforms a high-level specification of the computation into high-performance parallel code, tailored to the characteristics of the target architecture  ...  Depending on the circumstances, the synthesised code could also call highly-tuned, machine-specific Basic Linear Algebra Subprograms (BLAS) libraries, or optimized low-level functions from the existing  ... 
doi:10.1109/sc.2002.10056 dblp:conf/sc/BaumgartnerBCHHLNPRS02 fatcat:hd4ayjqhofhc5hx6cmovvthw5y

Binary synthesis

Greg Stitt, Frank Vahid
2007 ACM Transactions on Design Automation of Electronic Systems  
We compare binary synthesis to several related areas of research, and we then describe the key technologies required for effective binary synthesis: decompilation techniques necessary for binary synthesis  ...  to achieve results competitive with source-level synthesis, hardware/software partitioning methods necessary to find critical binary regions suitable for synthesis, synthesis methods for converting regions  ...  Binary synthesis can also generate hardware for library code which traditional approaches are unable to do because libraries are generally provided in object code format.  ... 
doi:10.1145/1255456.1255471 fatcat:ch3da4ypozfetgij2y2j6ecweq

Bridging the Gap Between General-Purpose and Domain-Specific Compilers with Synthesis

Alvin Cheung, Shoaib Kamil, Armando Solar-Lezama, Marc Herbstritt
2015 Summit on Advances in Programming Languages  
Each kernel translator is associated with a domain-specific compiler, and the role of each kernel translator is to scan the input code in search of code fragments that can be optimized by the domain-specific  ...  By leveraging general synthesis technology, it is possible to have a generic kernel translator that can be specialized by compiler developers for each domainspecific compiler, making it easy to build new  ...  extend the system to other domains for which high-performance DSLs are available.  ... 
doi:10.4230/lipics.snapl.2015.51 dblp:conf/snapl/CheungKS15 fatcat:lqcelmyyfrcmhatjowolqgdihi

Program Generation for Small-Scale Linear Algebra Applications [article]

Daniele G. Spampinato, Paolo Bientinesi
2018 arXiv   pre-print
Internally, SLinGen uses synthesis and DSL-based techniques to optimize at a high level of abstraction.  ...  The output of SLinGen is performance-optimized single-source C code, optionally vectorized with intrinsics.  ...  obtains competitive or superior performance to handwritten code.  ... 
arXiv:1805.04775v1 fatcat:njapmbp6x5e6jhqweynev3hkwy

Leveraging Parallel Data Processing Frameworks with Verified Lifting

Maaz Bin Safeer Ahmad, Alvin Cheung
2016 Electronic Proceedings in Theoretical Computer Science  
Given a sequential code fragment, Casper uses verified lifting to infer a high-level summary expressed in our program specification language that is then compiled for execution on Hadoop.  ...  This rewriting-tedious and error-prone-also requires developers to choose the framework that best optimizes performance given a specific workload.  ...  Acknowledgement The authors are grateful for the support of NSF grants CNS-1563788, IIS-1546083, and DARPA award FA8750-16-2-0032.  ... 
doi:10.4204/eptcs.229.7 fatcat:xtv5syiinrcfvm6wlp5l72ohna

From relational verification to SIMD loop synthesis

Gilles Barthe, Juan Manuel Crespo, Cesar Kunz, Sumit Gulwani, Mark Marron
2013 Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '13  
Our synthesis technique is applicable to a wide range of loops, consistently produces performant SIMD code, and generates correctness proofs for the output code.  ...  We present a new program synthesis based technique for auto-vectorizing performance critical innermost loops.  ...  Acknowledgments We would like to thank the PPoPP reviewers and Rastislav Bodik for their constructive comments and thoughts on this work.  ... 
doi:10.1145/2442516.2442529 dblp:conf/ppopp/BartheCKGM13 fatcat:dke54m2jgje2nhfpf5sf5bt4j4

AnyHLS: High-Level Synthesis with Partial Evaluation [article]

M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leissa, Sebastian Hack, Jürgen Teich, Frank Hannig
2020 arXiv   pre-print
Then, vendor-specific HLS code is generated for Intel and Xilinx FPGAs. Portability is obtained by avoiding any vendor-specific pragmas at the source code.  ...  In order to validate achievable gains in productivity, a library for the domain of image processing is introduced as a case study, and its synthesis results are compared with several state-of-theart Domain-Specific  ...  Many thanks to our colleague Puya Amiri for his work on the pipeline support.  ... 
arXiv:2002.05796v2 fatcat:bi2qasacbzg47a42reufudwxo4

From relational verification to SIMD loop synthesis

Gilles Barthe, Juan Manuel Crespo, Sumit Gulwani, Cesar Kunz, Mark Marron
2013 SIGPLAN notices  
Our synthesis technique is applicable to a wide range of loops, consistently produces performant SIMD code, and generates correctness proofs for the output code.  ...  We present a new program synthesis based technique for auto-vectorizing performance critical innermost loops.  ...  Acknowledgments We would like to thank the PPoPP reviewers and Rastislav Bodik for their constructive comments and thoughts on this work.  ... 
doi:10.1145/2517327.2442529 fatcat:w2vktstyqveipdvq6eeffocgzu

A Comparative Evaluation of High-Level Hardware Synthesis Using Reed–Solomon Decoder

Abhinav Agarwal, Man Cheuk Ng, Arvind
2010 IEEE Embedded Systems Letters  
We present an implementation in Bluespec, a high-level HDL, and show a 7.8 improvement in performance while using only 0.45 area of a C-based implementation.  ...  Due to the presence of run-time dependencies, sometimes it is not clear how the C code can be restructured so that a synthesis tool can infer the desired hardware structure.  ...  Hicks and G. Raghavan at Nokia for their assistance.  ... 
doi:10.1109/les.2010.2055231 fatcat:riaqukwobjgzjoccfe4c7wqwqi

Loop Optimization (Dagstuhl Seminar 18111)

Sebastian Hack, Paul H. J. Kelly, Christian Lengauer, Michael Wagner
2018 Dagstuhl Reports  
The seminar brought together experts from three areas: (1) model-based loop optimization, chiefly, in the polyhedron model, (2) rewriting and program transformation, and (3) metaprogramming and symbolic  ...  Its aim was to review the 20+ years of progress since the Dagstuhl Seminar 9616 "Loop Parallelization" in 1996 and identify the challenges that remain.  ...  for high-performance computing.  ... 
doi:10.4230/dagrep.8.3.39 dblp:journals/dagstuhl-reports/HackKL18 fatcat:ms75ouezgreirnhsr7dk2i7bo4

M3: Semantic API Migrations [article]

Bruce Collie, Philip Ginsbach, Jackson Woodruff, Ajitha Rajan, Michael O'Boyle
2020 arXiv   pre-print
Then, we use an SMT-based code search engine to discover similar code in user applications. These discovered instances provide potential locations for API migrations.  ...  To tackle this problem, this paper proposes a novel approach (M^3), where probabilistic program synthesis is used to semantically model the behavior of library functions.  ...  The second case 2 highlights the utility of M 3 : after performing inlining, the code that explicitly calls strncpy is no different to code that performs an explicit loop.  ... 
arXiv:2008.12118v1 fatcat:wqzks3q2bfhgngul3jeymisjbq

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

Mostafa W. Numan, Braden J. Phillips, Gavin S. Puddy, Katrina Falkner
2020 IEEE Access  
During hardware synthesis, Catapult performs a number of optimisations including loop unrolling, loop merging and pipelining.  ...  Two backends produce cycle-accurate SystemC code for simulation and profiling, and VHDL code for FPGA synthesis.  ... 
doi:10.1109/access.2020.3024098 fatcat:hk7s2deq6zgp5fnuwvm5k6jodu
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