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Express Cube Topologies for on-Chip Interconnects

Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
Third, we introduce Generalized Express Cubes -a framework for expressing the space of on-chip interconnects -and demonstrate how existing and proposed topologies can be mapped to it.  ...  Scalability of on-chip interconnect topologies is critical to meeting these demands.  ...  To better understand the space of on-chip interconnects, we propose Generalized Express Cubes (GEC) -a framework that extends k-ary n-cubes with concentration and ex-press channels -and demonstrate how  ... 
doi:10.1109/hpca.2009.4798251 dblp:conf/hpca/GrotHKM09 fatcat:yay3vegdfra3bfbtu5mrt35daa

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

W.S. Lacy, J.L. Cruz-Rivera, D.S. Wills
1998 IEEE Transactions on Parallel and Distributed Systems  
Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.  ...  chip-to-chip wires for data signals.  ...  ACKNOWLEDGEMENTS We wish to thank Sudhakar Yalamanchili for reviewing a draft of this paper and for his insightful feedback during several discussions.  ... 
doi:10.1109/71.722222 fatcat:dtwoffijljcvljq7e7fezzkmza

Affordable Scalability Using Multi-Cubes [chapter]

Håkon Bugge, Knut Omang
1999 Lecture Notes in Computer Science  
We analyze the scalability of r-ary f-cube topologies built from state-of-the-art SCI technology.  ...  We show how the SCI ringlets and bus used for packet switching dimensions limits scalability of the interconnect, and how the two relates to each other.  ...  The topology addressed in this paper will be direct networks based on r-ary f-cubes, or multidimensional toruses, also called multicubes.  ... 
doi:10.1007/10704208_11 fatcat:bxwhuyspurcivobv6xqccejj7e

Comparison Between Topological Properties Of Hyperx And Generalized Hypercube For Interconnection Networks

Sadoon Azizi, Naser Hashemi, Mohammad Amiri Zarandi
2014 Journal of Mathematics and Computer Science  
Different topologies have been proposed for interconnection networks in literature. The Generalized Hypercube is one of the oldest topologies that can be mentioned.  ...  Recently a group of researchers at HP Lab have introduced a new topology for these networks, called HyperX.  ...  Our main contribution in this paper is extracting some aspects of off-chip HyperX topology using mathematical expressions.  ... 
doi:10.22436/jmcs.09.02.04 fatcat:ill5byxtezefddgsca47sd2hli

Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs

Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna, Kyung-Hoae Koo, Li-Shiuan Peh, Krishna C. Saraswat
2010 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip  
[14] ) for large node count on-chip networks.  ...  In this paper, we compare a particular physical express topology (express physical channels (EPC) based on express cubes [4] ), to a virtual express topology proposal (express virtual channels (EVC)  ... 
doi:10.1109/nocs.2010.26 dblp:conf/nocs/ChenAKKPS10 fatcat:6jqlnohinnecvd7swnocafmxjq

On-chip implementation of multiprocessor networks and switch fabrics

Terry Tao Ye, Giovanni De Micheli
2008 International Journal of Embedded Systems  
On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon floorplan.  ...  Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC network topologies are regular.  ...  ., 2003) is one design example that uses 4-ary fat-tree topology for the MPSoC on-chip communication.  ... 
doi:10.1504/ijes.2008.022392 fatcat:4qmhz2u7mvcmnphgevwp63lmju

A Cost and Performance Analytical Model for Large-Scale On-Chip Interconnection Networks

Takanori Kurihara, Yamin Li
2016 2016 Fourth International Symposium on Computing and Networking (CANDAR)  
As an interconnection topology, two-dimensional mesh is widely used in the design of the network-on-chip (NoC) for integrating dozens of processing elements (PEs).  ...  However, as the progress of IC technology, it becomes possible to integrate a large-scale system on a chip that contains more than one thousand PEs.  ...  the costperformance of on-chip interconnection networks based on the topological properties, architecture, and IC layout characteristics.  ... 
doi:10.1109/candar.2016.0083 dblp:conf/ic-nc/KuriharaL16 fatcat:nmqrgwvuo5d5pe4zr2dyrwhbky

Performance evaluation of wormhole routed network processor-memory interconnects

T. Kocak, J. Engel
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
We utilize our customdesigned, event-driven, interconnect simulator to evaluate the performance of wormhole routed packet-based off-chip k-ary n-cube interconnect architectures for line cards.  ...  Our performance results show that wormhole routed k-ary n-cube based interconnect topologies significantly outperform the existing line card interconnects and they are able to sustain higher traffic loads  ...  Results show that k-ary n-cube based topologies significantly outperforms the current solutions on network line cards.  ... 
doi:10.1109/ipdps.2006.1639641 dblp:conf/ipps/KocakE06 fatcat:v4omw3rkwjczxdvokzopth4fgm

A case for routing cache on HPC switches

Shin-ichi Ishida, Michihiro Koibuchi, Hiroaki Nishi
2012 IEICE Communications Express  
Routing decision based on off-chip CAM (Content Addressable Memory)-based table lookup imposes a significant delay, however, using on-chip small routing cache can bypass it when it hits.  ...  Large many-core parallel applications become sensitive to communication latencies, suggesting the need for low-latency networks in high-performance computing systems.  ...  The commodity HPC interconnect, as known as system area network (SAN), usually accepts arbitrary topologies [3, 4] .  ... 
doi:10.1587/comex.1.49 fatcat:fb6ynmbltvgfxbtxfanyrruuay

An Efficient Dynamic Parallel and Distributed Network with Hybrid Hyper Cube

Venkat Reddy P
2020 International Journal of Advanced Trends in Computer Science and Engineering  
In this manuscript, we suggest another hybrid interconnection network topology named "Hybrid Hyper Cube (HHC)"that will be a result of two old style mainstream interconnection geographies to be specific  ...  The interconnection network topology is the very significant contemplations in plan of equal frameworks as it is spine network over that the various parts of PC speak with one another.  ...  The strategy is a conveyed one, as each sound hub close to a bombed one plays out a similar technique freely and concurrently. At that point the reliability expression for the cube is determined.  ... 
doi:10.30534/ijatcse/2020/147942020 fatcat:fw76mz2eeramxjk5ayzjy6ur3m

Express virtual channels

Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
on-chip networks.  ...  Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the pervasive communication fabric  ...  Dally of Stanford University for useful feedback on this work. We would also like to thank Ted Tabe and David V.  ... 
doi:10.1145/1250662.1250681 dblp:conf/isca/KumarPKJ07 fatcat:u52fqwexjvc5dou5vhxqa5my7i

Express virtual channels

Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
2007 SIGARCH Computer Architecture News  
on-chip networks.  ...  Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the pervasive communication fabric  ...  Dally of Stanford University for useful feedback on this work. We would also like to thank Ted Tabe and David V.  ... 
doi:10.1145/1273440.1250681 fatcat:sfnctlndq5a2zgzbdc67m62fle

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks

Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh
2006 Computer Design (ICCD '99), IEEE International Conference on  
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs).  ...  In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, highbandwidth network-on-chip (NoC) fabrics.  ...  ACKNOWLEDGMENTS We thank Sharad Malik of Princeton, Andrew Kahng of UC San Diego, and Dennis Sylvester of the University of Michigan for early discussions on the motivation and goals of a system-level  ... 
doi:10.1109/iccd.2006.4380806 dblp:conf/iccd/SoteriouEWLP06 fatcat:djuclqr32vhxrbm6hfch3tgjzu

Energy characteristic of a processor allocator and a network-on-chip

Dawid Zydek, Henry Selvaraj, Grzegorz Borowik, Tadeusz Łuba
2011 International Journal of Applied Mathematics and Computer Science  
Energy characteristic of a processor allocator and a network-on-chip Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs.  ...  Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs.  ...  Similar to the 2D-mesh, a k-ary 2-cube has regular physical arrangements that make it well suited for an on-chip layout.  ... 
doi:10.2478/v10006-011-0029-7 fatcat:cby3q2ucczczzpdknrm5lwk2ly

Off-chip communication architectures for high throughput network processors

Jacob Engel, Taskin Kocak
2009 Computer Communications  
We also developed an event-driven, interconnect simulation framework to evaluate the performance of packet-based off-chip k-ary n-cube interconnect architectures for line cards.  ...  Our performance results show that k-ary n-cube topologies, and especially our modified version of 2-ary 3-cube interconnect -the 3D-mesh, significantly outperform existing line card interconnects and are  ...  Express cube provide short cuts for messages traveling long distances.  ... 
doi:10.1016/j.comcom.2008.12.043 fatcat:n44wcdfjgjhzji5tzqgx2abo3q
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