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Exploring trade-offs between performance and resource requirements for synchronous dataflow graphs

Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal
2009 2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia  
Trade-off analysis between resource usage and performance is critical in the life cycle of those products, from tailoring platforms to target applications at design time to resource management at runtime  ...  Synchronous dataflow graphs (SDFGs) are widely used to model streaming applications such as signal processing and multimedia applications.  ...  Those techniques cannot be applied to trade-off analysis between resources and performance for SDFGs.  ... 
doi:10.1109/estmed.2009.5336821 dblp:conf/estimedia/YangGBSC09 fatcat:kdmt5oxhzzdmtiw4oxogjmemla

Predictable dynamic embedded data processing

Marc Geilen, Sander Stuijk, Twan Basten
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient  ...  Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time.  ...  [15] explores trade-offs between time and memory usage for memory architectures for data storage and transfer.  ... 
doi:10.1109/samos.2012.6404194 dblp:conf/samos/GeilenSB12 fatcat:oskdckwjujexxhj5dyraehmuqa

Dataflow modeling and design for cognitive radio networks

Lai-Huei Wang, Shuvra S. Bhattacharyya, Aida Vosoughi, Joseph R. Cavallaro, Markku Juntti, Jani Boutellier, Olli Silven, Mikko Valkama
2013 8th International Conference on Cognitive Radio Oriented Wireless Networks  
As RF frequency agility and reconfiguration for carrier aggregation are important goals for 4G LTE Advanced systems, we also focus on dataflow analysis for digital pre-distortion algorithms.  ...  Dataflow modeling will be important to provide a layer of abstraction and will be applied to generate flexible baseband representations for cognitive radio testbeds, including the Rice WARP platform.  ...  and trade-off exploration.  ... 
doi:10.1109/crowncom.2013.6636817 dblp:conf/crowncom/WangBVCJBSV13 fatcat:sop5pmoe7ra23n5tue3uhtqp6y

An integrated hardware/software design methodology for signal processing systems

Lin Li, Carlo Sau, Tiziana Fanni, Jingui Li, Timo Viitanen, François Christophe, Francesca Palumbo, Luigi Raffo, Heikki Huttunen, Jarmo Takala, Shuvra S. Bhattacharyya
2019 Journal of systems architecture  
Using the proposed methodology, we apply and integrate a variety of dataflow graph optimizations that are important for efficient mapping of the DNN system into a resource constrained implementation that  ...  While automated techniques, such as those referred to above for scheduling and buffer mapping, are effective for specialized combinations of platforms and dataflow models (e.g., multicore CPUs and synchronous  ...  supported in part by Business Finland (FiDiPro project StreamPro1846/31/2014); US National Science Foundation (CNS1514425); H2020 Program CERBERO (# 732105), ALOHA (# 780788), FitOptiVis (# 783162) Projects; and  ... 
doi:10.1016/j.sysarc.2018.12.010 fatcat:owkfwvndxbcqzpukk3v4i63ine

Buffer management for multi-application image processing on multi-core platforms: Analysis and case study

Dong-Ik Ko, Nara Won, Shuvra S. Bhattacharyya
2010 2010 IEEE International Conference on Acoustics, Speech and Signal Processing  
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient management of buffer memory is  ...  To address this problem, this paper develops new modeling and analysis techniques based on dataflow representations, and demonstrates these techniques on a multi-core implementation case study involving  ...  This paper addresses trade-offs between shared buffer configurations and inter-core communication performance.  ... 
doi:10.1109/icassp.2010.5495515 dblp:conf/icassp/KoWB10 fatcat:dv7u4qemgzcsvfg5essckfuqsu

Modeling methodology for integrated simulation of embedded systems

Akos Ledeczi, James Davis, Sandeep Neema, Aditya Agrawal
2003 ACM Transactions on Modeling and Computer Simulation  
Non-functional requirements are captured as formal, application-specific constraints. MILAN has integrated tool support for design-space exploration and pruning.  ...  Formal metamodels and explicit constraints define the domain-specific modeling language developed for MILAN that combines hierarchical, heterogeneous, parametric dataflow representation with strong data  ...  Deriving simulations at multiple-levels of granularity helps the system designer in performing rapid trade-off decisions and helps elevate time-to-market pressures.  ... 
doi:10.1145/778553.778557 fatcat:ybtdhcmjlffdzkavd5x7wk4354

A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour

Sander Stuijk, Marc Geilen, Twan Basten
2010 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools  
Synchronous Dataflow Graphs (SDFGs) provide predictability and are often used to model time-constrained streaming applications that are mapped onto a multiprocessor platform.  ...  The design flow generates a set of mappings that provide a trade-off in their resource usage.  ...  Next, these trade-off spaces are combined into a single trade-off space for the application graph.  ... 
doi:10.1109/dsd.2010.31 dblp:conf/dsd/StuijkGB10 fatcat:vhvrlvveevgqte7btxtbjd4xbe

An integrated ASIP design flow for digital signal processing applications

Vladimir Guzma, Shuvra S. Bhattacharyya, Pertti Kellomaki, Jarmo Takala
2008 2008 First International Symposium on Applied Sciences on Biomedical and Communication Technologies  
In this paper, we develop an integration of SDF-and ASIP-oriented design flows, and use this integrated design flow to explore trade-offs in the space of hardware/software implementations.  ...  One such MoC is Synchronous Dataflow (SDF), which is used increasingly in the design and implementation of signal processing applications.  ...  ACKNOWLEDGMENT This work was supported by the Academy of Finland, project 205743, and the Finnish Funding Agency for Technology and Innovation under research funding decision 40163/07.  ... 
doi:10.1109/isabel.2008.4712585 fatcat:dvghmalvpnbyveutk6sugmvbu4

Prototyping scalable digital signal processing systems for radio astronomy using dataflow models

N. Sane, J. Ford, A. I. Harris, S. S. Bhattacharyya
2012 Radio Science  
Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library.  ...  We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.  ...  We acknowledge with thanks the contributions of Shilpa Bollineni, Srikanth Bussa, Randy Mc-Cullough, Scott Ransom, and Jason Ray of the National Radio Astronomy Observatory.  ... 
doi:10.1029/2011rs004924 fatcat:y6q6bwsvufbhnhladpomhncjr4

Hardware/Software Cosynthesis of DSP Systems [chapter]

Shuvra Bhattacharyya
2001 Signal Processing and Communications  
Thus, we do not explore techniques for fine-grain cosynthesis [21] , including synthesis of applicationspecific instruction processors (ASIPs) [43] , nor do we explore cosynthesis for control-dominant  ...  performance analysis [36, 49, 54] .  ...  The alternative synchronization graphs represented in Figure 11 offer a variety of latency/throughput trade-off alternatives for implementing the given schedule.  ... 
doi:10.1201/9780203908068.ch8 fatcat:z2tvsup2f5adtehjabmyop6jpi

FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques

Hojin Kee, Shuvra S. Bhattacharyya, Ian Wong, Yong Rao
2010 2010 IEEE International Conference on Acoustics, Speech and Signal Processing  
Synchronous dataflow (SDF) is an ubiquitous dataflow model of computation that has been studied extensively for efficient simulation and software synthesis of DSP applications.  ...  In recent years, parameterized SDF (PSDF) has evolved as a useful framework for modeling SDF graphs in which arbitrary parameters can be changed dynamically.  ...  Synchronous dataflow (SDF) [2] has been used widely as an efficient model of computation (MOC) to analyze performance and resource requirements when implementing DSP algorithms on various kinds of target  ... 
doi:10.1109/icassp.2010.5495504 dblp:conf/icassp/KeeBWR10 fatcat:xwexrat7xfdjrlzwjoi2ghcxjq

Multithreaded Simulation for Synchronous Dataflow Graphs

Chia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya
2011 ACM Transactions on Design Automation of Electronic Systems  
Synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems.  ...  The traditional approach for simulating SDF graphs is to compute and execute static single-processor schedules.  ...  ordering, and buffering for trading off between throughput, synchronization overhead, and buffer requirements.  ... 
doi:10.1145/1970353.1970358 fatcat:pj5tadkr3bewvmeln53s66geuu

Multithreaded simulation for synchronous dataflow graphs

Chia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
Synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems.  ...  The traditional approach for simulating SDF graphs is to compute and execute static single-processor schedules.  ...  ordering, and buffering for trading off between throughput, synchronization overhead, and buffer requirements.  ... 
doi:10.1145/1391469.1391553 dblp:conf/dac/HsuPB08 fatcat:ebc3tefyt5h2vhyicufff74v6q

Iteration-Based Trade-Off Analysis of Resource-Aware SDF

Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal
2011 2011 14th Euromicro Conference on Digital System Design  
Trade-off analysis between performance and resource usage of SDFGs allows designers to explore implementation alternatives of a system while meeting its performance requirements and resource constraints  ...  We present a new approach to explore the trade-offs in a such systems. It breaks analysis down in iterations of dataflow graph execution and uses a max-plus algebra semantics.  ...  CONCLUSION In this paper, we investigate a novel technique to explore the resource usage vs. performance trade-offs in dataflow graphs with shared resources using an iteration-based state-space exploration  ... 
doi:10.1109/dsd.2011.78 dblp:conf/dsd/YangGBSC11 fatcat:s4xnb6n3jnf5risywxyfe6hmhu

A methodology for optimizing buffer sizes of dynamic dataflow fpgas implementations

Ab Al-Hadi Ab Rahman, Simone Casale-Brunet, Claudio Alberti, Marco Mattavelli
2014 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
The paper presents an heuristic capable of finding a close-to-minimum buffer size configuration for deadlockfree executions, and a methodology to efficiently explore different configurations for feasible  ...  Minimizing buffer sizes of dynamic dataflow implementations without introducing deadlocks or reducing the design performance is in general an important and useful design objective.  ...  ≤ B(x β ) ≤ B(x max β ) such that a feasible trade-off between performance and overall memory requirement is identified.  ... 
doi:10.1109/icassp.2014.6854554 dblp:conf/icassp/RahmanBAM14 fatcat:ustipfc2qjai7a7ehyc2hrz73e
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