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Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors

J. Sahuquillo, S. Petit, A. Pont, V. Milutinović
2005 Journal of systems architecture  
To check the performance two different scenarios are considered: a superscalar processor and a symmetric multiprocessor.  ...  The obtained results show that (i) in the superscalar processor the split data caches perform similarly or better than larger conventional caches, (ii) some splitting schemes work well in multiprocessors  ...  cache needed to achieve the same performance as the corresponding split data cache scheme. in symmetric multiprocessors (SMPs).  ... 
doi:10.1016/j.sysarc.2004.12.002 fatcat:4jdsqp6ipzc6tdshyk7y6cxg74

Multithreaded Processors

T. Ungerer
2002 Computer journal  
The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance.  ...  [120] : a shared-main-memory multiprocessor (i.e. the typical symmetric multiprocessor today), a shared-secondary-cache multiprocessor and a shared-primary-cache multiprocessor.  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm

Multi-Threaded Processors [chapter]

David Padua, Amol Ghoting, John A. Gunnels, Mark S. Squillante, José Meseguer, James H. Cownie, Duncan Roweth, Sarita V. Adve, Hans J. Boehm, Sally A. McKee, Robert W. Wisniewski, George Karypis (+29 others)
2011 Encyclopedia of Parallel Computing  
The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance.  ...  [120] : a shared-main-memory multiprocessor (i.e. the typical symmetric multiprocessor today), a shared-secondary-cache multiprocessor and a shared-primary-cache multiprocessor.  ... 
doi:10.1007/978-0-387-09766-4_423 fatcat:heb3n2cfwnbi5nvxv5kvxd2xgm

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
Several multithreaded processors are announced by industry or already into production in the areas of high-performance microprocessors, media, and network processors.  ...  The contexts of two or more threads of control are often stored in separate on-chip register sets.  ...  ACKNOWLEDGMENTS The authors would like to thank anonymous reviewers for many valuable comments.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi

A shared reconfigurable VLIW multiprocessor system

Fakhar Anjam, Stephan Wong, Faisal Nadeem
2010 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)  
This multiprocessor design is based on our earlier ρ-VEX processor design. Since the ρ-VEX processor is a parameterized processor, our multiprocessor design is also parameterized.  ...  In this paper, we present the design and implementation of an open-source reconfigurable very long instruction word (VLIW) multiprocessor system.  ...  For the dual-processor system, the input data is split into two sets each of 1024 bytes. Each processor is provided its own data set and the same application for encryption/decryption runs on it.  ... 
doi:10.1109/ipdpsw.2010.5470734 dblp:conf/ipps/AnjamWN10 fatcat:kv7gdsryjfhtve52ntylhep4gm

Database Servers on Chip Multiprocessors: Limitations and Opportunities

Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson, Naju Mancheril, Anastassia Ailamaki, Babak Falsafi
2007 Conference on Innovative Data Systems Research  
At the same time, high levels of integration have enabled the advent of chip multiprocessors and increasingly large (and slow) on-chip caches.  ...  In this paper we characterize the performance of a commercial database server running on emerging chip multiprocessor technologies.  ...  Finally, we thank the CIDR reviewers for their valuable feedback in early drafts of this paper.  ... 
dblp:conf/cidr/HardavellasPJMAF07 fatcat:nej2yv6vwzhgllzc6ijp23rpdu

Fifty years of microprocessor evolution: from single CPU to multicore and manycore systems

Goran Nikolic, Bojan Dimitrijevic, Tatjana Nikolic, Mile Stojcev
2022 Facta universitatis - series Electronics and Energetics  
The performance of today's processors implemented on a single chip surpasses the performance of a room-sized supercomputer from just 50 years ago, which cost over $ 10 million [1].  ...  The main components of a modern microprocessor are a number of general-purpose cores, a graphics processing unit, a shared cache, memory and input-output interface and a network on a chip to interconnect  ...  Acknowledgement: This work was supported by the Serbian Ministry of Education and Science, Project No TR-32009 -"Low power reconfigurable fault-tolerant platforms".  ... 
doi:10.2298/fuee2202155n fatcat:mvz44nhglfcfxp4mx6z3ttygdi

Design methodology for pipelined heterogeneous multiprocessor system

Seng Lin Shee, Sri Parameswaran
2007 Proceedings - Design Automation Conference  
Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design.  ...  Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g.  ...  Area cost include the base processor, instruction & data caches and the TIE instructions.  ... 
doi:10.1145/1278480.1278682 dblp:conf/dac/SheeP07 fatcat:4nzslpengnayfb37aoxalhqotu

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Seng Lin Shee, Parameswaran
2007 Proceedings - Design Automation Conference  
Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design.  ...  Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g.  ...  Area cost include the base processor, instruction & data caches and the TIE instructions.  ... 
doi:10.1109/dac.2007.375276 fatcat:egr5npxrbrcbbbzc6opzq4tfna

Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Kunle Olukotun, Lance Hammond, James Laudon
2007 Synthesis Lectures on Computer Architecture  
More critically, the on-chip cache hierarchy of the multiprocessor is significantly different from the cache hierarchy of the 6-way superscalar processor.  ...  Simulation Results One of the major causes of processor stalls in a superscalar processor is cache misses.  ...  His areas of expertise include multithreading, multiprocessors, and performance modelling.  ... 
doi:10.2200/s00093ed1v01y200707cac003 fatcat:qyjilavdhfcmlnc46l5sxg7ssq

Verification-Aware Microprocessor Design

Anita Lungu, Daniel J. Sorin
2007 Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on  
Using Cadence SMV, a composite formal verification tool that combines model checking and theorem proving, we explore several aspects of processor design, including caches, TLBs, pipeline depth, ALUs, and  ...  The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable.  ...  Try to avoid performing operations on only part of an otherwise symmetric variable.  ... 
doi:10.1109/pact.2007.4336202 fatcat:2234v5g6ejhahblumiv5ch4ot4

The Wisconsin Wind Tunnel project

Mark D. Hill, James R. Larus, David A. Wood
1994 SIGARCH Computer Architecture News  
This document lists contributors to the Wisconsin Wind Tunnel Project, gives a brief description of the project, and presents references and abstracts to its principal papers, including how to obtain them  ...  on-line.  ...  This paper discusses the problem of cache-conscious structure definition and explores two techniques-structure field reordering and structure splitting-that address this.  ... 
doi:10.1145/192537.192543 fatcat:rvtgkgeonnba3cdbociaiglrdq

Accelerating Multiprocessor Simulation with a Memory Timestamp Record

K.C. Barr, H. Pan, M. Zhang, K. Asanovic
2005 IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.  
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestamp record (MTR).  ...  Both MTR and a multiprocessor version of functional fast-forwarding (FFW) make similar performance estimates, usually within 15% of our detailed model.  ...  Given the write and read timestamps, one can infer either of the following scenarios: (1) the read request results in a cache hit and the data remains modified, or (2) the data is evicted and written back  ... 
doi:10.1109/ispass.2005.1430560 dblp:conf/ispass/BarrPZA05 fatcat:bnsfxw65kjhorof2fdxvmw7wiu

Comprehensive hardware and software support for operating systems to exploit MP memory hierarchies

Chun Xia, J. Torrellas
1999 IEEE transactions on computers  
Finally, a cost-performance comparison of these schemes suggests that the most cost-effective ones are code layout optimization and block operation support, while the least cost-effective one is software  ...  In this paper, we evaluate a comprehensive set of hardware and software supports that minimize the performance losses for the operating system in a sophisticated cache hierarchy.  ...  ACKNOWLEDGMENTS We thank the referees and the graduate students in the I-ACOMA group for their feedback.  ... 
doi:10.1109/12.769432 fatcat:4hbtey6n6jfpbpqef73xu6rame

Multiprocessor System-on-Chip (MPSoC) Technology

W. Wolf, A.A. Jerraya, G. Martin
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade.  ...  This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture.  ...  ACKNOWLEDGMENT The authors would like to thank B. Ackland and S. Dutta for the helpful discussions of their MPSoCs.  ... 
doi:10.1109/tcad.2008.923415 fatcat:p37pvh5iezfdjd4acepney4zmy
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