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Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
2006
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
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In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architecture. ...
This algorithm targets on a flexible architecture template which permits experimental exploration over different architecture alternatives. ...
Acknowledgements We thank the European Social Fund (ESF), Operational Program for Educational and Vocational Training II (EPEAEK II), and particularly the Program HERAKLEITOS, for funding the above work ...
doi:10.1109/ipdps.2006.1639349
dblp:conf/ipps/DimitroulakosGG06
fatcat:b5s6j57tvzgtvk5tabvb4shozq
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures
[chapter]
2000
Lecture Notes in Computer Science
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Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. ...
Based on the KressArray architecture family, a design-space exploration system is being implemented, which supports the designer in finding an appropriate architecture for a given application domain. ...
Conclusions An interactive approach for the design-space exploration of mesh-based reconfigurable architectures from the KressArray family has been presented. ...
doi:10.1007/3-540-44614-1_42
fatcat:ks3tm2eb35eurkghtynfpbsnsi
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
[chapter]
2000
Lecture Notes in Computer Science
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Based on the KressArray architecture family, a design-space exploration system is being implemented, which supports the designer in finding an appropriate architecture featuring an optimized performance ...
Coarse-grain reconfigurable architectures promise to be more adequate for computational tasks due to their better efficiency and higher speed. ...
Conclusions An interactive approach for the design-space exploration of mesh-based reconfigurable architectures from the KressArray family has been presented. ...
doi:10.1007/3-540-45373-3_12
fatcat:fqupauzbcne5haq4dhqbfm7l5a
Hardware Cost Analysis for Weakly Programmable Processor Arrays
2006
2006 International Symposium on System-on-Chip
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Coarse-grained reconfigurable architectures support a high degree of parallelism at multiple levels. ...
In this paper technology-independent hardware cost analysis for a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is performed ...
ACKNOWLEDGMENT This project is supported in part by the German Science Foundation (DFG) in project under contract TE 163/13-1. ...
doi:10.1109/issoc.2006.321996
dblp:conf/issoc/KisslerHKT06
fatcat:ira6n7n3qfac7ib5j7vd7gszgm
A highly parameterizable parallel processor array architecture
2006
2006 IEEE International Conference on Field Programmable Technology
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In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed. ...
The applicability of our approach is tested in a case study with different interconnect topologies on an FPGA platform. ...
ACKNOWLEDGMENT This project is supported in part by the German Science Foundation (DFG) in project under contract TE 163/13-1. ...
doi:10.1109/fpt.2006.270293
dblp:conf/fpt/KisslerHKT06
fatcat:k6woefmcnjcypjc6h4t2p6fqju
EGRA: A Coarse Grained Reconfigurable Architectural Template
2011
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Index Terms-Coarse grained reconfigurable architectures (CGRAs), design space exploration. ...
Most CGRA design emerged in research present ad-hoc solutions in many aspects; in this paper we propose an architectural template to enable design space exploration of different possible CGRA designs. ...
ACKNOWLEDGMENT The authors would like to thank the Advanced Learning and Research Institute (ALaRI), Lugano, Switzerland, for the technical support. ...
doi:10.1109/tvlsi.2010.2044667
fatcat:7psqlsnmb5g3flv2swuwtc6pny
A Review on Embedded FPGAs Architectures and Configuration Tools
2019
Turkish Journal of Electrical Engineering and Computer Sciences
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An eFPGA must be well-designed and accompanied by an optimized CAD tool suite to respond to target application's requirements in terms of power consumption, area, and performance. ...
In this survey, we studied coarse-grained eFPGAs with customized blocks which are used for domain-specific applications and fine-grained eFPGAs that are used for general purposes but have lower performance ...
Acknowledgment This work is supported by Computer and Embedded Systems Laboratory and Digital Research Center of Sfax. ...
doi:10.3906/elk-1901-193
fatcat:kimby27rrbfyte4t2bh3lqtg3q
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems
2012
7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
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The Architecture oriented par-aLlelization for high performance embedded Multi-core systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of ...
Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware -introduced by software parallelism of multiple cores and the flexibility of reconfigurable ...
ACKNOWLEDGMENT This work is co-funded by the European Union under the 7th Framework Programme under grant agreement ICT-287733. ...
doi:10.1109/recosoc.2012.6322879
dblp:conf/recosoc/StripfOBKHBRSKDMKMGAVDMSGP12
fatcat:ztmty66zq5d3hol7j5fenoxcxa
Design of Reusable Context Pipelining for Coarse Grained Reconfigurable Architecture
2018
International Journal for Research in Applied Science and Engineering Technology
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A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units. ...
CGRAs are a well-researched topic and the design space of a CGRA is quite large. ...
COARSE GRAINED RECONFIGURABLE ARCHITECTURE A recent trend in the architectural platforms for embedded systems is the adoption of Reconfigurable computing elements for cost, performance, and flexibility ...
doi:10.22214/ijraset.2018.4596
fatcat:6q4jpnj2e5emhgf2m57pfszrti
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
2009
Microprocessors and microsystems
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In this survey we explore the field of coarse-grained reconfigurable computing on the basis of the hardware aspects of granularity, reconfigurability, and interconnection networks, and discuss the effects ...
We classify the coarse-grained reconfigurable architectures into four categories and present some of the existing examples of these categories. ...
Dan Hammerstrom) for their valuable feedback during the internal review of the paper. ...
doi:10.1016/j.micpro.2008.10.003
fatcat:k4c63f4k2zbc5a4mfr3vfwqkfe
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures
2008
2008 Design, Automation and Test in Europe
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Most of the research initiatives taken in this area have resorted to a template-based approach, where the structure of the reconfigurable architecture is partially fixed with several tunable parameters ...
Coarse-Grained Re-configurable Architecture (CGRA), a strongly emerging class, is currently receiving due attention for offering excellent performance as well as flexibility post fabrication. ...
In order to compare between different architectural styles, we first modelled, in a limited way, the well-known coarse-grained reconfigurable architectures. ...
doi:10.1109/date.2008.4484864
dblp:conf/date/ChattopadhyayCILAM08
fatcat:j6q4dktl5ffqzn4u2k6dwugj64
Review of recent trends in Coarse Grain Reconfigurable Architectures for signal processing applications
2018
Advances in Systems Science and Applications
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Coarse grained reconfigurable architecture got the attention of researchers working in designing computing architectures for processing massive streaming data associated with the multimedia applications ...
The reconfigurable architectures are designed to exploit the regular and repetitive structure of signal processing algorithms and the coarse grained processing elements are designed to match with the word ...
COARSE GRAIN RECONFIGURABLE ARCHITECTURES FOR DSP The paradigm shift happened in the IC design space is that it changed from a two dimensional problem of area and speed to a three dimensional problem of ...
doi:10.25728/assa.2018.18.1.508
fatcat:eihxjjbe5fbtfidecoa4j7sv6y
Communication-Oriented Design Space Exploration for Reconfigurable Architectures
2007
EURASIP Journal on Embedded Systems
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However, there is no generic tool to perform such an exploration for coarse-grain or heterogeneous-grain architectures, just a small number of very specific tools are able to explore a limited set of architectures ...
To address this major lack, in this paper we propose a new design space exploration approach adapted to fine-and coarse-grain granularities. ...
This work permits the consideration of fine-grain, coarse-grain, and heterogeneous architectures for the same application. The designer can explore a large domain in the reconfigurable design space. ...
doi:10.1155/2007/23496
fatcat:r3byspfuq5hdzlpocaqbykyrau
Communication-Oriented Design Space Exploration for Reconfigurable Architectures
2007
EURASIP Journal on Embedded Systems
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However, there is no generic tool to perform such an exploration for coarse-grain or heterogeneous-grain architectures, just a small number of very specific tools are able to explore a limited set of architectures ...
To address this major lack, in this paper we propose a new design space exploration approach adapted to fine-and coarse-grain granularities. ...
This work permits the consideration of fine-grain, coarse-grain, and heterogeneous architectures for the same application. The designer can explore a large domain in the reconfigurable design space. ...
doi:10.1186/1687-3963-2007-023496
fatcat:y6weazz5ofcxtdvwtf2nd77tca
Coarse-Grained Reconfigurable Array: Architecture and Application Mapping
2011
IPSJ Transactions on System LSI Design Methodology
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Xplorer 27) is an interactive design space exploration (DSE) environment that assists the user in optimizing the architecture of KressArray for a given application domain, considering KressArray as an ...
Figure 14 shows the DRESC (Dynamically Reconfigurable Embedded System Compiler) framework that has been suggested in Refs. 28) and 31) to explore the architecture design space and generate a good instance ...
He is also interested in computer architecture and especially in configurable and reconfigurable computer architecture design. ...
doi:10.2197/ipsjtsldm.4.31
fatcat:46ph7de3wreexmn6wl3ealzzhy
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