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Exploring early and late ALUs for single-issue in-order pipelines

Alen Bardizbanyan, Per Larsson-Edefors
2015 2015 33rd IEEE International Conference on Computer Design (ICCD)  
We then go on to evaluate what is the most efficient way to make use of two ALUs, one early and one late ALU, which is a technique that has revitalized commercial in-order processors in recent years.  ...  Second, the position of the ALU inside the pipeline impacts the branch penalty. This paper considers the question on how to best make use of ALU resources inside a single-issue in-order pipeline.  ...  With the ultimate goal to improve performance and energy metrics, this work is concerned with design tradeoffs for the ALU resources in a single-issue in-order pipeline.  ... 
doi:10.1109/iccd.2015.7357163 dblp:conf/iccd/BardizbanyanL15 fatcat:hbznxxct3nhrbjbnd33edzn7km

EOLE

Arthur Perais, André Seznec
2014 SIGARCH Computer Architecture News  
Fortunately, VP also implies that many single-cycle ALU instructions have their operands predicted in the front-end and can be executed in-place and in-order.  ...  Furthermore, since Value Prediction in itself usually increases performance, our resulting {Early | Out-of-Order | Late} Execution architecture (EOLE), is often more efficient than a baseline VP-augmented  ...  Ahuja et al. showed that partial bypassing could greatly impediment performance, even for a simple in-order single-issue pipeline [1] .  ... 
doi:10.1145/2678373.2665742 fatcat:4tapabt7pffgvm2j5hcxdgabti

EOLE: Paving the way for an effective implementation of value prediction

Arthur Perais, Andre Seznec
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
Fortunately, VP also implies that many single-cycle ALU instructions have their operands predicted in the front-end and can be executed in-place and in-order.  ...  Furthermore, since Value Prediction in itself usually increases performance, our resulting {Early | Out-of-Order | Late} Execution architecture (EOLE), is often more efficient than a baseline VP-augmented  ...  Ahuja et al. showed that partial bypassing could greatly impediment performance, even for a simple in-order single-issue pipeline [1] .  ... 
doi:10.1109/isca.2014.6853205 dblp:conf/isca/PeraisS14 fatcat:s7ly2chn2jgpta6yh3425bzoaq

EOLE

Arthur Perais, André Seznec
2016 ACM Transactions on Computer Systems  
Fortunately, VP also implies that many single-cycle ALU instructions have their operands predicted in the front-end and can be executed in-place, in-order.  ...  Furthermore, since Value Prediction in itself usually increases performance, our resulting {Early -Out-of-Order -Late} Execution architecture, EOLE, is often more efficient than a baseline VP-augmented  ...  [Ahuja et al. 1995] showed that partial bypassing could greatly impede performance, even for a simple in-order single-issue pipeline.  ... 
doi:10.1145/2870632 fatcat:k5weq3zt6fdfbivpidi5hc232q

Microarchitectural Transformations Using Elasticity

Marc Galceran-Oms, Alexander Gotmanov, Jordi Cortadella, Mike Kishinevsky
2011 ACM Journal on Emerging Technologies in Computing Systems  
Elasticity is a paradigm that tolerates the variations in computation and communication delays.  ...  This article reveals how elasticity can be effectively and practically used to derive pipelined circuits by using correct-byconstruction transformations that can be fully automated.  ...  If the microarchitecture issues ALU instructions most of the time, the throughput is close to 1, since data dependencies can always use forwarding in order to avoid stalls.  ... 
doi:10.1145/2043643.2043648 fatcat:66od7s6xcrf6hfktske3ztjyly

CRIB

Erika Gunadi, Mikko H. Lipasti
2011 SIGARCH Computer Architecture News  
This paper advocates in-place execution of instructions, a power-saving, pipeline-free approach that consolidates rename, issue, and bypass logic into one structure-the CRIB-while simultaneously eliminating  ...  the need for a multiported register file, instead storing architected state in a simple rank of latches.  ...  ACKNOWLEDGEMENTS This work was supported in part by NSF award CCF-0702272, financial support from IBM, and equipment donations from HP.  ... 
doi:10.1145/2024723.2000068 fatcat:5jrz47rv6ngxplvufmp7wrqkeu

Zero-cycle loads: microarchitecture support for reducing load latency

T.M. Austin, G.S. Sohi
1995 Proceedings of the 28th Annual International Symposium on Microarchitecture  
We evaluate these designs in a number of contexts: with and without software support, in-order vs. out-of-order issue, and on architectures with many and few registers.  ...  We present two pipeline designs supporting zero-cycle loads: one for pipelines with a single stage of instruction decode, and another for pipelines with multiple decode stages.  ...  This work was supported in part by NSF Grants CCR-9303030 and MIP-9505853, ONR Grant N00014-93-1-0465, and a donation from Intel Corp.  ... 
doi:10.1109/micro.1995.476815 dblp:conf/micro/AustinS95 fatcat:u4duppwmuje2jl2sgthdoyp6sy

On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE

Fernando A. Endo, Arthur Perais, André Seznec
2017 ACM Transactions on Architecture and Code Optimization (TACO)  
The EOLE microarchitecture and D-VTAGE value predictor were recently introduced to solve practical issues of value prediction (VP).  ...  In this study, we present a detailed evaluation of the potential of VP in the context of EOLE/D-VTAGE and different compiler options.  ...  ACKNOWLEDGMENTS The authors would like to thank Kleovoulos Kalaitzidis, Biswabandan Panda, and anonymous reviewers for their comments and suggestions.  ... 
doi:10.1145/3090634 fatcat:cyirodjinbeizhigti5ez7mhvq

Calipers: A Criticality-aware Framework for Modeling Processor Performance [article]

Hossein Golestani, Rathijit Sen, Vinson Young, Gagan Gupta
2022 arXiv   pre-print
Calipers can model in-order and out-of-order microarchitectures, structural hazards, and different types of ISAs, and can evaluate multiple ideas in a single run.  ...  late-stage design space exploration without recompiling and rerunning the program.  ...  To model limited issue bandwidth and execution schedule, Calipers needs to obtain an issue order for instructions, i.e., order for E vertices. In-order Core.  ... 
arXiv:2201.05884v1 fatcat:pa3djk74mngkbc6et745aiumqu

Concurrency-Enhancing Transformations for Asynchronous Behavioral Specifications: A Data-Driven Approach

John Hansen, Montek Singh
2008 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems  
operation and unnecessary sequencing.  ...  While they provide rapid design times, the performance of the resulting implementations is typically limited, in part because specifications written by designers often have limited concurrency due to unpipelined  ...  Optimization Technique Original Parallel Pipelined Parallel+Pipelined Area (µm) 2 Lines (n) Area (µm) 2 Lines (n) Area (µm) 2 Lines (n) Area (µm) 2 Lines (n)  ... 
doi:10.1109/async.2008.20 dblp:conf/async/HansenS08 fatcat:kzec32hsjzd67nzwa7bmlop7fu

Design of a High Performance VLSI Processor [chapter]

John L. Hennessy, Norman P. Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross
1983 Third Caltech Conference on Very Large Scale Integration  
However, to achieve high performance from that processor, the architecture and implementation must be carefully designed and tuned.  ...  Current VLSI fabrication technology makes it possible to design a 32-bit CPU on a single chip.  ...  Acknowledgments Many people have contributed to the MIPS project; especially worthy of note are John Gill, Forest Baskett, and Jud Leonard.  ... 
doi:10.1007/978-3-642-95432-0_3 fatcat:ga53jb5k2zhphn7wju25yweh7u

High performance RISC microprocessors

J. Choquette, M. Gupta, D. McCarthy, J. Veenstra
1999 IEEE Micro  
We have implemented two Montage incarnations now on the market: the SR1 and the SR1-GX high-performance microprocessor cores. Other designs are in the pipeline.  ...  SandCraft recognized this challenge early on and developed the Montage architecture to meet these needs and generate revenue that fuels business growth.  ...  The pipeline stages are not simu-lated while in fast mode.  ... 
doi:10.1109/40.782567 fatcat:vehrfcamdndh5fxelu2cyjm2le

End-to-End Verification of Processors with ISA-Formal [chapter]

Alastair Reid, Rick Chen, Anastasios Deligiannis, David Gilday, David Hoyes, Will Keen, Ashan Pathirane, Owen Shepherd, Peter Vrabel, Ali Zaidi
2016 Lecture Notes in Computer Science  
The return on investment issues include the need to start catching bugs early in development, the need to continue catching bugs throughout development, and the need to be able to reuse verification IP  ...  This is an end-to-end framework to detect bugs in the datapath, pipeline control and forwarding/stall logic of processors.  ...  ; and they cover micro-architectures ranging from 3-stage, in-order pipelines through dual-issue, in-order pipelines to out-of-order pipelines.  ... 
doi:10.1007/978-3-319-41540-6_3 fatcat:jaht4ofh4ngblkks2sxs3pujnq

Exploiting fine-grained parallelism through a combination of hardware and software techniques

Stephen Melvin, Yale Patt
1991 Proceedings of the 18th annual international symposium on Computer architecture - ISCA '91  
In order to exploit this parallelism, a combination of hardware and software techniques must be applied.  ...  We will show that indeed for narrow instruction words 1itde is to be gained b y appl yi ng these techniques.  ...  (late in the window).  ... 
doi:10.1145/115952.115981 dblp:conf/isca/MelvinP91 fatcat:3egzyuktezcxnby3mypoufmbqe

Scalable selective re-execution for EDGE architectures

Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler
2004 Proceedings of the 11th international conference on Architectural support for programming languages and operating systems - ASPLOS-XI  
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines.  ...  the issue of loads.  ...  ACKNOWLEDGMENTS We thank Professor Anant Agarwal for his comments on an initial draft of the paper.  ... 
doi:10.1145/1024393.1024408 dblp:conf/asplos/DesikanSBK04 fatcat:xmtndwqiejarlifgphsfstvgmy
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