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A scalable architecture for visual data exploration

Jonathan Decker, Alex Godwin, Mark A. Livingston, Denise Royle
2009 2009 IEEE Symposium on Visual Analytics Science and Technology  
We propose a component-based visualization architecture that is built specifically to encourage the flexible exploration of geospatial event databases.  ...  Our proposed system aims to address the limited scalability associated with coordinated multiple views (CMVs) through the implementation of an efficient core application which is meant to be extended by  ...  CONCLUSION AND FUTURE WORK The system we have proposed is the foundation for a truly scalable architecture which will allow for visual exploration of large, high-dimensional, complex, and dynamic datasets  ... 
doi:10.1109/vast.2009.5333451 dblp:conf/ieeevast/DeckerGLR09 fatcat:m24crriu45gplmemn7btssmofe

A Transparently Scalable Visualization Architecture for Exploring the Universe

Chi-wing Fu, Andrew J. Hanson
2007 IEEE Transactions on Visualization and Computer Graphics  
as a powerful tool for modeling, rendering, navigation, and exploration in this gigantic space.  ...  data sets give us three-dimensional information for a wide variety of astronomical objects, and, altogether, they provide the raw data for a three-dimensional virtual Universe that one can in principle explore  ...  Visualization methods exploring these quantities and implementing additional scalable architectures would be of further interest for science and education.  ... 
doi:10.1109/tvcg.2007.2 pmid:17093340 fatcat:xgur5ebzonam5nyl4nveo3lyky

Exploring Energy Scalability in Coprocessor-Dominated Architectures for Dark Silicon

Qiaoshi Zheng, Nathan Goulding-Hotta, Scott Ricketts, Steven Swanson, Michael Bedford Taylor, Jack Sampson
2014 ACM Transactions on Embedded Computing Systems  
Recent work has shown that automatically generated application-specific coprocessors can greatly improve energy efficiency, but it is not clear that current techniques will scale to Coprocessor-Dominated Architectures  ...  Scalable CoDA systems also use a tiled architecture for this reason and to distribute coprocessors among multiple memory and host interfaces.  ...  However, designing scalable CoDAs will raise numerous architectural challenges. Energy consumption from integration overheads grows as CoDAs scale, eroding potential savings.  ... 
doi:10.1145/2584657 fatcat:pvkgf2jbynf7zkdw2257y6zq2y

He-P2012: Architectural heterogeneity exploration on a scalable many-core platform

Francesco Conti, Chuck Pilkington, Andrea Marongiu, Luca Benini
2014 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors  
heterogeneity exploration -Allows relatively effortless exploration of HW/SW deployment schemes -Supports multiple programming models on the SW side due to the flexible, lightweight HWPE control• An embodiment  ...  programming models Easy exploration of HW/SW deployment 20 Applications 2.HW architecture: He-P2012 3.HW/SW codesign: SIDL 4.Using He-P2012: CV apps 1.Introduction 5.Conclusions Face Detection  ... 
doi:10.1109/asap.2014.6868645 dblp:conf/asap/ContiPMB14 fatcat:sfdis5ww6zegjjlwfscuz7mlv4

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis [article]

Carlos Vega, Jose Fernando Zazo, Hugo Meyer, Ferad Zyulkyarov, Sergio Lopez Buedo, Javier Aracil
2017 arXiv   pre-print
In this paper we study the feasibility of using disaggregated architectures for intensive data applications, in contrast to the monolithic approach of server-oriented architectures.  ...  Heterogeneous data centers are pushing towards more cost-efficient architectures with better resource provisioning.  ...  and also exploring hybrid switching architectures.  ... 
arXiv:1709.06127v1 fatcat:2s35nlqb3fhg7cy5zqvddi7cfu

A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration

Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
2012 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors  
In this paper, we present a reconfigurable hardware methodology for efficient parallel processing of large-scale graph exploration problems.  ...  Our methodology is based on a reconfigurable hardware architecture which decouples computation and communication while keeping multiple memory requests in flight at any given time, taking advantage of  ...  Reconfigurable hardware architecture template The overall architecture of the reconfigurable computing solution, as illustrated in Figure 1 , resembles a scalable, many-core style processor architecture  ... 
doi:10.1109/asap.2012.30 dblp:conf/asap/BetkaouiWTL12 fatcat:masycdtex5g6jgo3drv74aswta

Accurate, scalable and informative design space exploration for large and sophisticated multi-core oriented architectures

Chang-Burm Cho, J. Poe, Tao Li, Jingling Yuan
2009 2009 IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems  
In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration  ...  IPC and power) of monolithic architecture design, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across  ...  ACKNOWLEDGMENT This work is supported in part by NSF CAREER Award CCF-0845721, and by Microsoft Research Safe and Scalable Multi-core Computing Award.  ... 
doi:10.1109/mascot.2009.5366283 dblp:conf/mascots/ChoPLY09 fatcat:npsknlayezc65h6w4plxnjtcqu

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

Carlos Vega, Jose Fernando Zazo, Hugo Meyer, Ferad Zyulkyarov, S. Lopez-Buedo, Javier Aracil
2017 2017 IEEE 19th International Conference on High Performance Computing and Communications; IEEE 15th International Conference on Smart City; IEEE 3rd International Conference on Data Science and Systems (HPCC/SmartCity/DSS)  
In this paper we study the feasibility of using disaggregated architectures for intensive data applications, in contrast to the monolithic approach of server-oriented architectures.  ...  Heterogeneous data centers are pushing towards more cost-efficient architectures with better resource provisioning.  ...  and also exploring hybrid switching architectures.  ... 
doi:10.1109/hpcc-smartcity-dss.2017.45 dblp:conf/hpcc/VegaZMZLA17 fatcat:fwks6vicwnfftbjnmwquaxjnlu

Exploring the VLSI scalability of stream processors

B. Khailany, W.J. Dally, S. Rixner, U.J. Kapasi, J.D. Owens, B. Towles
The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.  
This paper explores the scalability of stream architectures to future VLSI technologies where over a thousand floating-point units on a single chip will be feasible.  ...  Recent work has shown these processors to be more area-and energy-efficient than conventional programmable architectures.  ...  In this paper we explore the feasibility of scaling stream processors to thousands of ALUs.  ... 
doi:10.1109/hpca.2003.1183534 dblp:conf/hpca/KhailanyDRKOT03 fatcat:moqh4uqp3nhmjnvbscgmoj5jhi

A Case for Visualization-Integrated System-Level Design Space Exploration [chapter]

Andy D. Pimentel
2005 Lecture Notes in Computer Science  
We further explain that these techniques must be scalable and interactive, allowing designers to better explore complex (embedded system) architectures.  ...  System-level simulation frameworks that aim for early design space exploration create large volumes of simulation data in exploring alternative architectural solutions.  ...  We explain that the visualization techniques must be scalable and interactive, allowing designers to better explore complex architectures that may be heterogeneous in nature and may exploit various levels  ... 
doi:10.1007/11512622_48 fatcat:wvgbuwdpbvfurgenwkoqbnejtm

Exploiting memory allocations in clusterised many-core architectures

Rafael Garibotti, Luciano Ost, Anastasiia Butko, Ricardo Reis, Abdoulaye Gamatié, Gilles Sassatelli
2019 IET Computers & Digital Techniques  
First, this work reviews the current literature on memory allocations and explores the limitations of cluster-based many-core architectures.  ...  is the most appropriate for future mobile architectures.  ...  Unlike, our work extends both simple analyses by exploring the scalability, performance and energy efficiency of different memory allocations in emerging clusterised many-core architectures.  ... 
doi:10.1049/iet-cdt.2018.5136 fatcat:ldr7obabxbdwnemdq2l34iywtq

Automated scalability testing of software as a service

Paulo Moura, Fabio Kon
2013 2013 8th International Workshop on Automation of Software Test (AST)  
Scalability has been studied in several areas of Computer Science and scalability testing and evaluation of contemporary software systems is an active topic.  ...  In this paper, we introduce a flexible and extensible framework for automated scalability testing of software offered as a service and propose to evaluate the scalability using hypothesis tests.  ...  Our next step in the evolution of this Scalability Explorer is to provide a better evaluation of the relation between workload and architecture.  ... 
doi:10.1109/iwast.2013.6595784 dblp:conf/icse/MouraK13 fatcat:5fapss6x7jbjzoc2a3yx3osvlu

SHAPES:

Pier S. Paolucci, Ahmed A. Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires".  ...  The SW challenge is to provide a simple and efficient programming environment for tiled architectures.  ...  The feedback from the retargetable compiler, we allow to explore the architectural optimization of the computational tiles.  ... 
doi:10.1145/1176254.1176297 dblp:conf/codes/PaolucciJLTV06 fatcat:7wfok5rve5h3tnblow4nrnpqeq

Tier-scalable reconnaissance: the challenge of sensor optimization, sensor deployment, sensor fusion, and sensor interoperability

Wolfgang Fink, Thomas George, Mark A. Tarbell, Thomas George, Zhongyang Cheng
2007 Micro (MEMS) and Nanotechnologies for Defense and Security  
The tier-scalable paradigm integrates multi-tier (orbit atmosphere surface/subsurface) and multi-agent (satellite UAV/blimp surface/subsurface sensing platforms) hierarchical mission architectures, introducing  ...  To support such mission architectures, a high degree of operational autonomy is required.  ...  Thus, to achieve the significantly higher benefits afforded by the tier-scalable reconnaissance architecture, the individual systems that make up the architecture ideally must themselves be miniaturized  ... 
doi:10.1117/12.721486 fatcat:lsr6op2robfpxcgqaihwh75b44

A scalable and compact systolic architecture for linear solvers

Kevin S. H. Ong, Suhaib A. Fahmy, Keck-Voon Ling
2014 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors  
Finally, the scalable design can be adapted to different sized problems with minimum effort.  ...  We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition.  ...  Lastly, a comparison study of the proposed architecture against other GPU and floating point DSP implementations will be explored. Fig. 1 : 1 Comparison of Triangular Systolic Array Architecture II.  ... 
doi:10.1109/asap.2014.6868658 dblp:conf/asap/OngFL14 fatcat:3j23w7boyffb7issoqhobvblei
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