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Teaching computer architecture using an architecture description language
2004
Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04
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ArchC enables students to perform several experiments using its automatically generated SystemC simulators, covering topics from simple single-cycle (functional) models to pipeline and memory hierarchy ...
The simplicity and flexibility of the ADL, along with its simulation features, proved to be an useful tool not only for research, but also for computer architecture education. ...
We are also very grateful to all the students and teachers that are using ArchC, for education and/or research, whose feedback has been extremely valuable to the continuous improvement in ArchC tools. ...
doi:10.1145/1275571.1275580
dblp:conf/wcae/RigoJAAC04
fatcat:ucsobfersng4hkntn2mch65454
Scalability evaluation in many-core systems due to the memory organization
2016
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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The goal of this paper is to highlight the limitations of shared memory connected through a network-on-chip (NoC) in many-core systems, executing a similar workload with both memory organizations. ...
SM has a worst traffic distribution, with hotspots around the SM, and a much higher communication volume compared to DM. ...
The main goal is to describe the platform in a high-level abstraction, enabling the designer to explore and to evaluate new architectures with automatic generation software tools and simulators. ...
doi:10.1109/icecs.2016.7841216
dblp:conf/icecsys/MadalozzoDAM16
fatcat:qbevxpxcujggzfhruhmzqyxddi
ACCGen: An Automatic ArchC Compiler Generator
2012
2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing
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exploration in early stages of the design. ...
They compare, as well, the generated code quality with LLVM and gcc, two well-known open-source compilers. ...
We conducted this experiment in an Intel Core 2 Quad Q6600 with 4GB RAM memory. ...
doi:10.1109/sbac-pad.2012.33
dblp:conf/sbac-pad/AulerCB12
fatcat:cliw4wd54nfm3ogzhkhwbubeyi
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
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Considering a standalone execution, i.e., the processor with an internal memory running the software in the same single core machine mentioned above, compiled with GCC 4.0 with full optimization, the interpreted ...
The ArchC Reference Platform The ArchC Reference Platform (ARP) born like a reference model to guide ArchC [1, 2] users on how to ex-plore ArchC 2.0 TLM communications capabilities in order to build ...
doi:10.1109/isvlsi.2007.9
dblp:conf/isvlsi/MacielARAA07
fatcat:t7z2heb3bneofma53bvfm4bcbi
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation
2012
Journal of systems architecture
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A cycle accurate description of the memory hierarchy (memory cache, memory latency, etc.) is not presented in this paper and is still a work in progress. ...
Harmless is 8% faster but does not model the memory hierarchy. Simulation times are in the same order of magnitude. ...
doi:10.1016/j.sysarc.2012.05.001
fatcat:oyo7na2ckzbs5oi4vnor3ua4p4
A Combined Optimization Method for Tuning Two-Level Memory Hierarchy Considering Energy Consumption
2011
EURASIP Journal on Embedded Systems
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In this paper we combined two optimization methods for tuning both instruction and data cache configurations in a two-level memory hierarchy, where both levels have separate instruction and data caches ...
Experiments based on simulations were performed for 12 applications from the Mibench suite benchmark and the combined method achieved better efficiency in 60% of the evaluated cases compared with existing ...
Basically, the TECH heuristic is similar to TCaT, but it adopts a reverse exploration order and a different exploration environment based on the Architecture Description Language known as ArchC. ...
doi:10.1155/2011/620578
fatcat:qxpi45v4x5gnzeb5gqu4r63ckm
An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms
2011
International Journal of Reconfigurable Computing
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Thus, developing new high-level specification mechanisms for the reduction of the design effort with automatic architecture exploration is a necessity. ...
PCacheEnergyAnalyzer has been validated with several applications of Mibench, Mediabench, and PowerStone benchmarks, and results show that it provides analysis with reduced simulation effort. ...
This heuristic uses the eCACTI [20] cache memory model to determine the energy consumption of the memory hierarchy. ...
doi:10.1155/2011/219497
fatcat:vsdfqvs27ncxtj6v7awxujxsny
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration
2006
Proceedings of the Design Automation & Test in Europe Conference
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Among them, the difficulty of thoroughly exploring the design space by simultaneously sweeping axes like processing elements, memory hierarchies and chip interconnect fabrics. ...
openness and flexibility in terms of design space exploration. 1 ...
One axis of exploration involves memory hierarchies, where both the partitioning among local (e.g. caches) and higher-latency memories and the partitioning among private and shared buffers have to be investigated ...
doi:10.1109/date.2006.244000
dblp:conf/date/AngioliniCLFFB06
fatcat:kjfkgmhbyfcgrpvfxfvwvbh3qq
Fast Translated Simulation of ASIPs
2011
Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
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If the output would be only one single function, then, in the the case of large target application, the function would become uncompilable (e.g. problems with optimizations, problems with virtual memory ...
The designer can describe resources, such as memories or registers, instruction set and its behavior. The behavior is described with SystemC functions in shared libraries. ...
doi:10.4230/oasics.memics.2010.93
dblp:conf/memics/PrikrylKHK10
fatcat:epql3ez54nfdjpuelszsqdq6nm
Modeling and simulating memory hierarchies in a platform-based design methodology
Proceedings Design, Automation and Test in Europe Conference and Exhibition
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Making use of the new architecture description language ArchC, able to capture the processor description as well as the memory subsystem configuration, this environment offers support for system-level ...
As a case study, it is presented the memory architecture exploration for a simple image processing application, yet a more robust environment evaluation is performed through the execution of some real-world ...
Figure 2 . 2 Memory hierarchy in ArchC.
Figure 3 . 3 Performance of media benchmarks. ...
doi:10.1109/date.2004.1268953
dblp:conf/date/VianaBRAA04
fatcat:g2hiejwotvfxbphinbrzn6lixq
Generating and evaluating application-specific hardware extensions
[article]
2014
arXiv
pre-print
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architecture in terms of operation set and memory model on custom instruction generation/selection under different input/output constraints. ...
YARDstick is a building block for ASIP development, integrating application analysis, custom instruction generation and selection with user-defined compiler intermediate representations. ...
Functional and cycle-accurate simulators generated by version 1.5.1 of ArchC can be used with YARDstick without any modifications. ...
arXiv:1403.7380v1
fatcat:zqlxls245vd77bs7mrhfaiaz6m
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip
2007
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)
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versions of the PowerPC, Leon2 and ARM7 RISC processors; • interconnections in terms of bus and Networks-On-Chip; • memory hierarchies including simple memories and caches. ...
Then, simulation can be automatically stopped and it is possible to explore the internal state of the architecture and compare it with the state of the golden model. ...
doi:10.1109/dft.2007.35
dblp:conf/dft/BeltrameBFMS07
fatcat:by3mdg7yjjafvizv652ar5vnlq
Managing Complexity through Abstraction: A Refinement-Based Approach to Formalize Instruction Set Architectures
[chapter]
2011
Lecture Notes in Computer Science
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Current industrial practice is to describe a processor's ISA informally using natural language often with added semi-formal notation to capture the functional intent of the instructions. ...
Our method is now being used to formalize the ISA of the XMOS XCore processor with the aim to guarantee that the documentation of the XCore matches the silicon and the silicon matches the architectural ...
This allows design development and exploration within a hierarchy of increasingly detailed abstraction levels. ...
doi:10.1007/978-3-642-24559-6_39
fatcat:uxwodbnbcvc3dfaf4dpf2swqde
0 Instruction Set Architecture
[chapter]
2003
Digital Design and Computer Organization
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The global memory hierarchy has not been taken into account in these processor designs, and is decided in the ASAM project by the macro-level exploration in cooperation with a separate global memory system ...
hierarchy. ...
3b 4 Loading information from APEX file ... 5 Initial prototype has 3 issue -slots 6 7 Searching for best 'ed ' fitness solution ... 8 Using ' issue -slot --first ' strategy Listing A.8: Example exploration ...
doi:10.1201/b12403-15
fatcat:mygaz2meibgljew5tzvmuw6x5i
Hardware-Accelerated Cross-Architecture Full-System Virtualization
2016
ACM Transactions on Architecture and Code Optimization (TACO)
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Hardware virtualization solutions provide users with benefits ranging from application isolation through server consolidation to improved disaster recovery and faster server provisioning. ...
For an ARM-based Linux guest system running on an x86 host with Intel VT support we demonstrate application performance levels, based on SPEC CPU2006 benchmarks, of up to 5.88× over state-of-the-art QEMU ...
In this example, the MMU is an x86-64 MMU, which has a 4-level hierarchy. Definition 3.7 (Native Page Definition 3.8 (Guest MMU). ...
doi:10.1145/2996798
fatcat:kefw3xgczzf7va3kw6opeaatim
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