Filters








8,130 Hits in 7.1 sec

Exploring efficient operating points for voltage scaled embedded processor cores

M. Buss, T. Givargis, N. Dutt
Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)  
@ S G ¦ x a $ " @ u f a 0 1 6 ¦ 1 n F A A a I Q a I W Q 3.2 Variable speed processors ¤ ) u ¦ ) Q Y ¦ ) a 3 F 1 1 ¦ a u a 6 Q S W 1 G ) !  ... 
doi:10.1109/real.2003.1253274 dblp:conf/rtss/BussGD03 fatcat:xwkqhbos4zccpmnwxemqhg7b34

Development of the Retargetable Tool Suite for Embedded Software

Ko Kwangman
2008 2008 Advanced Software Engineering and Its Applications  
low power/energy optimizer, system simulator and debugger through the proposed Embedded Processor Description Language(EPDL).  ...  In order to construct the most suitable embedded software development environment, we design and implements the Retargetable Tool Suite for Embedded Software(RTS-ES) composed of target code generator,  ...  An effective DVS algorithm is one that intelligently determines when to adjust the current frequency-voltage setting(scaling points) and to which frequency-voltage setting(scaling factors), so that considerable  ... 
doi:10.1109/asea.2008.10 fatcat:tbvpbmlbuzgp5bxu3aokwkfhii

A survey of techniques for improving energy efficiency in embedded computing systems

Sparsh Mittal
2014 International Journal of Computer Aided Engineering and Technology  
In this paper, we survey the techniques for managing power consumption of embedded systems.  ...  This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded  ...  For CMOS circuits, dynamic power is related with voltage and frequency as P ∝ F V 2 and hence, by reducing the frequency, the voltage at which the circuit needs to be operated for stable operation can  ... 
doi:10.1504/ijcaet.2014.065419 fatcat:r5kgr2rlnbaanca5mhgqwvicae

A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems [article]

Sparsh Mittal
2014 arXiv   pre-print
In this paper, we survey the techniques for managing power consumption of embedded systems.  ...  This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded  ...  For CMOS circuits, dynamic power is related with voltage and frequency as P ∝ F V 2 and hence, by reducing the frequency, the voltage at which the circuit needs to be operated for stable operation can  ... 
arXiv:1401.0765v1 fatcat:6lj7m34k6rcn3izdanqwfi35gu

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing [chapter]

Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini
2011 Lecture Notes in Computer Science  
This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist.  ...  The single-core architecture is composed of a processing core (PC), an instruction memory (IM) and a data memory (DM), while the multi-core architecture consists of PCs, individual IMs for each core, a  ...  [9] presented a new ultra low energy processor with low voltage operations for wireless monitoring systems.  ... 
doi:10.1007/978-3-642-24154-3_11 fatcat:ttfymygw4zadlcivofilinl7iy

A New Core Level Utilization Algorithm for Energy-Efficient Multicore Systems

2020 International Journal of Computers  
Also, Design metrics depend on, the manufacturers of semiconductor chips which, have implemented multicore processors to boost the level of energy efficiency by using verified techniques for voltage and  ...  This paper proposes a new algorithm to achieve energy-efficient by monitoring core energy and level utilization control such as: Increasing the number of cores to execute the task, scaling voltage, and  ...  Although all the cores for the CPU In both chips, each pair of cores (PMD-Processor MoDule), can work at the same voltage at different frequencies.  ... 
doi:10.46300/9108.2020.14.7 fatcat:fn4lkkw6cba3jc2qmk2l25r3fu

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Wenheng Ma, Qiao Cheng, Yudi Gao, Lan Xu, Ningmei Yu
2021 Micromachines  
Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core.  ...  In this paper, we evaluated the energy distribution in various embedded processors.  ...  Conclusions This paper has analyzed the power distributions of embedded processors with different architectures, and pointed out the key factors reducing energy efficiency.  ... 
doi:10.3390/mi12030292 pmid:33802187 fatcat:hn5o77cfvndvhe4dx7xbnlx3j4

Implementing low-power configurable processors - practical options and tradeoffs

J. Wei, C. Rowen
2005 Proceedings. 42nd Design Automation Conference, 2005.  
Third, automatic processor generation tools enable logic optimization, signal switching reductions, and seamless mapping into low-voltage circuits and processes, for very low-power operation.  ...  Finally, this work quantifies the dramatic process, voltage and temperature dependence in post-layout leakage power for small processor designs.  ...  Acknowledgements The authors are grateful for the helpful technical discussions with Jagesh Sanghavi, Eliot Gerstner, Eileen Peters Long, and Grant Martin of Tensilica, Dhrumil Gandhi of ARM and Dan Hillman  ... 
doi:10.1109/dac.2005.193903 fatcat:bydvgp6hdbfnxmazww4guhbegm

Implementing low-power configurable processors

John Wei, Chris Rowen
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
Third, automatic processor generation tools enable logic optimization, signal switching reductions, and seamless mapping into low-voltage circuits and processes, for very low-power operation.  ...  Finally, this work quantifies the dramatic process, voltage and temperature dependence in post-layout leakage power for small processor designs.  ...  Acknowledgements The authors are grateful for the helpful technical discussions with Jagesh Sanghavi, Eliot Gerstner, Eileen Peters Long, and Grant Martin of Tensilica, Dhrumil Gandhi of ARM and Dan Hillman  ... 
doi:10.1145/1065579.1065765 dblp:conf/dac/WeiR05 fatcat:cnb4nxzq2rd3dejxhekkudmasq

Simpler, more efficient design

Borivoje Nikolic
2015 ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)  
Rapid design flow maps generated modules into silicon and enables design-space exploration for optimal efficiency.  ...  This paper proposes several approaches for making the design process more efficient and enabling custom energyefficient integrated circuits.  ...  To achieve the same processing throughput as a single-core processor, the N-core processor can operate at roughly N-times lower clock rate, which allows for frequency scaling and significantly increased  ... 
doi:10.1109/esscirc.2015.7313819 dblp:conf/esscirc/Nikolic15 fatcat:tqsxgusdjzc5tbws2deheswziy

Energy-Efficient Subthreshold Processor Design

Bo Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester, D. Blaauw
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency.  ...  We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context.  ...  Additionally, since the core and the memory have different optimal operating points , it may be beneficial to design a system with separate supply and threshold voltages for the core and the memory [28  ... 
doi:10.1109/tvlsi.2008.2007564 fatcat:wz7yppqngzglhm4vngutvfbtcq

A control-theoretic approach to dynamic voltage scheduling

Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Jacob Bruce
2003 Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03  
The study is executionbased, not trace-based; the voltage-scaling heuristics were integrated into an embedded operating system running on a Motorola M-CORE processor model.  ...  Recent microprocessors have incorporated dynamic voltage scaling as a tool that system software can use to explore this trade-off.  ...  This architecture was chosen because it is one of the cutting edge embedded processors on the market today, and the M-CORE was designed for high performance and very low power operation.  ... 
doi:10.1145/951710.951744 dblp:conf/cases/VarmaGSCSB03 fatcat:flfeysl7rjctrhqkszakid66ui

A control-theoretic approach to dynamic voltage scheduling

Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Jacob Bruce
2003 Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03  
The study is executionbased, not trace-based; the voltage-scaling heuristics were integrated into an embedded operating system running on a Motorola M-CORE processor model.  ...  Recent microprocessors have incorporated dynamic voltage scaling as a tool that system software can use to explore this trade-off.  ...  This architecture was chosen because it is one of the cutting edge embedded processors on the market today, and the M-CORE was designed for high performance and very low power operation.  ... 
doi:10.1145/951741.951744 fatcat:uix7dx3mtvay3btd7g2qdzagzm

Run-time power and performance scaling with CPU-FPGA hybrids

Jose Nunez-Yanez, Arash Beldachi
2014 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
Adaptive voltage and frequency scaling obtained with embedded in-situ detectors is employed to scale performance and power in the FPGA fabric under processor control.  ...  Keywords-FPGA, energy efficient design, adaptive voltage scaling, energy propotional computing I. ~ 100% ~ 65% Performance increase Energy reduction  ...  For a given task, the lowest supply voltage of operation is experimentally derived and at run-time, voltage is adjusted to operate at this critical point.  ... 
doi:10.1109/ahs.2014.6880158 dblp:conf/ahs/Nunez-YanezB14 fatcat:jqbbyaevqrbofc6ovenbg5giyu

System level analysis of fast, per-core DVFS using on-chip switching regulators

Wonyoung Kim, Meeta S. Gupta, Gu-Yeon Wei, David Brooks
2008 High-Performance Computer Architecture  
Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control.  ...  Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order  ...  Scaling down the frequency of the processor slows down cpu-bound operations, but does not affect the time taken by memory-bound operations.  ... 
doi:10.1109/hpca.2008.4658633 dblp:conf/hpca/KimGWB08 fatcat:r3osegzwubdfvclqjrzfrafwqy
« Previous Showing results 1 — 15 out of 8,130 results