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Mapping Spiking Neural Networks to Neuromorphic Hardware [article]

Adarsha Balaji, Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Giacomo Indiveri, Jeffrey L. Krichmar, Nikil Dutt, Siebren Schaafsma, Francky Catthoor
2019 arXiv   pre-print
SpiNeCluster minimizes the number of spikes on global synapses, which reduces spike congestion on the shared interconnect, improving application performance.  ...  SpiNeCluster is a heuristic-based clustering technique to partition SNNs into clusters of synapses, where intracluster local synapses are mapped within crossbars of the hardware and inter-cluster global  ...  Our SpiNeMap design methodology allows simulating NoCs, segmented bus, and other interconnect topologies, facilitating future research on scalable interconnect for neuromorphic computing.  ... 
arXiv:1909.01843v1 fatcat:w4kpthbfcvbjpiw7oue7bxcpyq

NeuroXplorer 1.0: An Extensible Framework for Architectural Exploration with Spiking Neural Networks [article]

Adarsha Balaji and Shihao Song and Twisha Titirsha and Anup Das and Jeffrey Krichmar and Nikil Dutt and James Shackleford and Nagarajan Kandasamy and Francky Catthoor
2021 arXiv   pre-print
We present NeuroXplorer, a fast and extensible framework that is based on a generalized template for modeling a neuromorphic architecture that can be infused with the specific details of a given hardware  ...  Consequently, there is a growing need for an extensible simulation framework that can perform architectural explorations with SNNs, including both platform-based design of today's hardware, and hardware-software  ...  (a) A tile-based neuromorphic hardware [14] . A tile communicates spikes via the network switches (S) using a shared interconnect such as Networks-on-chip (NoC) [38] and Segmented Bus [7] .  ... 
arXiv:2105.01795v1 fatcat:yztiegjepvho5ecztv2akaj4vy

Reliability-Performance Trade-offs in Neuromorphic Computing [article]

Twisha Titirsha, Anup Das
2020 arXiv   pre-print
In this work, we demonstrate such trade-offs using a previously-proposed SNN mapping technique with 10 workloads from contemporary machine learning tasks for a state-of-the art neuromoorphic hardware.  ...  Neuromorphic architectures built with Non-Volatile Memory (NVM) can significantly improve the energy efficiency of machine learning tasks designed with Spiking Neural Networks (SNNs).  ...  ACKNOWLEDGMENT This work is supported by the National Science Foundation Award CCF-1937419 (RTML: Small: Design of System Software to Facilitate Real-Time Neuromorphic Computing).  ... 
arXiv:2009.12672v1 fatcat:5nr6vhxghjbrfi4a6auym4snpu

PyCARL: A PyNN Interface for Hardware-Software Co-Simulation of Spiking Neural Network [article]

Adarsha Balaji, Prathyusha Adiraju, Hirak J. Kashyap, Anup Das, Jeffrey L. Krichmar, Nikil D. Dutt, Francky Catthoor
2020 arXiv   pre-print
Second, we integrate cycle-accurate models of state-of-the-art neuromorphic hardware such as TrueNorth, Loihi, and DynapSE in PyCARL, to accurately model hardware latencies that delay spikes between communicating  ...  We show that system designers can also use PyCARL to perform design-space exploration early in the product development stage, facilitating faster time-to-deployment of neuromorphic products.  ...  In our prior work [23] , we have developed segmented bus interconnect for neuromorphic hardware using PyCARL.  ... 
arXiv:2003.09696v2 fatcat:k4oyr7r5srci5fylbbivw6kyom

An Analytical Comparison of Locally-Connected Reconfigurable Neural Network Architectures Using a C. elegans Locomotive Model

Jonathan Graham-Harper-Cater, Benjamin Metcalfe, Peter Wilson
2018 Computers  
is demonstrated as a critical component for matching the function and efficiency seen in biological networks.  ...  Furthermore, the concept of locality of connections is considered in more detail, highlighting the importance of dimensionality when designing neuromorphic architectures.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/computers7030043 fatcat:tn2rqwmfw5cyff7jybauczyg5u

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain [article]

Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings
2018 arXiv   pre-print
Thus, compared to conventional CPUs, these neuromorphic emulators are beneficial in many engineering applications such as for the porting of deep learning algorithms for various recognitions tasks.  ...  The goal of NE is to design systems capable of brain-like computation. Numerous large-scale neuromorphic projects have emerged recently.  ...  Figure 30 shows the possible opportunities in computing enabling both analog as well as neuromorphic computing.  ... 
arXiv:1805.08932v1 fatcat:xqtzbpp5ubhfrpfhj6sjffi6ii

Artificial neural networks in hardware: A survey of two decades of progress

Janardan Misra, Indranil Saha
2010 Neurocomputing  
We outline underlying design approaches for mapping an ANN model onto a compact, reliable, and energy efficient hardware entailing computation and communication and survey a wide range of illustrative  ...  We trace the recent trends and explore potential future research directions.  ...  The input signals are sent in their temporal order to an array of PEs for computing weight updates by means of an global optical broadcasting, thus taking advantage of fast optical communication as well  ... 
doi:10.1016/j.neucom.2010.03.021 fatcat:regzu6sshvekzd5wxcuaiytgqu

Neurogrid simulates cortical cell-types, active dendrites, and top-down attention [article]

Kwabena Boahen
2021 bioRxiv   pre-print
A central challenge for systems neuroscience and artificial intelligence is to understand how cognitive behaviors arise from large, highly interconnected networks of neurons.  ...  Due to the latter's serial operation, this approach has not scaled beyond millions of synaptic connections (per bus).  ...  Kauderer-Abrams for calibration algorithm development; B. Softky and H. S. Seung for assistance in editing the manuscript; and K. Chin for administrative support.  ... 
doi:10.1101/2021.05.14.444265 fatcat:qvzfitbo7vghrgoephpb4ydrmm

Accelerating pattern matching in neuromorphic text recognition system using Intel Xeon Phi coprocessor

Khadeer Ahmed, Qinru Qiu, Parth Malani, Mangesh Tamhankar
2014 2014 International Joint Conference on Neural Networks (IJCNN)  
for neuromorphic applications.  ...  Neuromorphic computing systems refer to the computing architecture inspired by the working mechanism of human brains.  ...  TABLE OF FIGURES Neuromorphic computing systems refer to the computing architecture inspired by the working mechanism and massive parallel structure of human brains.  ... 
doi:10.1109/ijcnn.2014.6889777 dblp:conf/ijcnn/AhmedQMT14 fatcat:mjqx3okkezbbdclzjljww7g5ve

A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

Jim Harkin, Fearghal Morgan, Liam McDaid, Steve Hall, Brian McGinley, Seamus Cawley
2009 International Journal of Reconfigurable Computing  
FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability.  ...  The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.  ...  Existing FPGAs limit the synaptic density achievable as they map biological synaptic computations onto arrays of digital logic blocks, which are not optimised in area or power consumption for scalability  ... 
doi:10.1155/2009/908740 fatcat:xzwbktrxjfampjmxnqozctp2ay

Memory and Information Processing in Neuromorphic Systems

Giacomo Indiveri, Shih-Chii Liu
2015 Proceedings of the IEEE  
As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists  ...  We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness  ...  Memory and computation are expressed in the dynamics of the circuits, and in the way they are interconnected.  ... 
doi:10.1109/jproc.2015.2444094 fatcat:enmuv4qr6bdktlh7t3rfwfj27i

Neuromorphic Architecture for the Hierarchical Temporal Memory

Abdullah M. Zyarah, Dhireesha Kudithipudi
2019 IEEE Transactions on Emerging Topics in Computational Intelligence  
There are few early explorations of the HTM hardware architecture, especially for the earlier version of the spatial pooler of HTM algorithm.  ...  These results indicate that the proposed architecture can serve as a digital core to build the HTM in hardware and eventually as a standalone self-learning system.  ...  ACKNOWLEDGMENT The authors would like to acknowledge Jeff Hawkins and Subutai Ahmed from Numenta in clarifying the HTM theory; Seagate for sponsoring part of this research; the reviewers for their time  ... 
doi:10.1109/tetci.2018.2850314 fatcat:biw7wb6darhkfghxy24u5fqquu

Comparing Neuromorphic Solutions in Action: Implementing a Bio-Inspired Solution to a Benchmark Classification Task on Three Parallel-Computing Platforms

Alan Diamond, Thomas Nowotny, Michael Schmuker
2016 Frontiers in Neuroscience  
Comparing neuromorphic solutions in action: implementing a bio-inspired solution to a benchmark classification task on three parallel-computing platforms Article (Published Version)  ...  Diamond, Alan, Nowotny, Thomas and Schmuker, michael (2016) Comparing neuromorphic solutions in action: implementing a bio-inspired solution to a benchmark classification task on three parallel-computing  ...  small items of data across a bus.  ... 
doi:10.3389/fnins.2015.00491 pmid:26778950 pmcid:PMC4705229 fatcat:ymdgs7fbu5hcpildkdmzp6hy4i

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Jose Ricardo Gomez-Rodriguez, Remberto Sandoval-Arechiga, Salvador Ibarra-Delgado, Viktor Ivan Rodriguez-Abdala, Jose Luis Vazquez-Avila, Ramon Parra-Michel
2021 Micromachines  
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip.  ...  Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/mi12020183 pmid:33673049 fatcat:mwlekxzfpfhwhbegwwyio4kaaq

An FPGA-based Massively Parallel Neuromorphic Cortex Simulator [article]

Runchun Wang, Chetan Singh Thakur, Andre van Schaik
2018 arXiv   pre-print
This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas  ...  With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.  ...  This allows HiAER-IFAT to be a general purpose neuromorphic platform for spike-based algorithms. Its scalability is therefore constrained by the size of the external memories.  ... 
arXiv:1803.03015v1 fatcat:xue5sz2xavdancqd3z4ytt5u6e
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