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Multi-layer software reliability for unreliable hardware

Muhammad Shafique, Philip Axer, Christoph Borchert, Jian-Jia Chen, Kuan-Hsun Chen, Björn Döbel, Rolf Ernst, Hermann Härtig, Andreas Heinig, Rüdiger Kapitza, Florian Kriebel, Daniel Lohmann (+4 others)
2015 it - Information Technology  
AbstractThis paper presents a multi-layer software reliability approach that leverages multiple software layers (e. g., programming language, compiler, and operating system) to improve the overall system  ...  reliability considering unreliable or partly-reliable hardware.  ...  at the circuit level, architecture-level masking, and program-level masking (e. g., due to the control and data flow).  ... 
doi:10.1515/itit-2014-1081 fatcat:q4vxxqgiznasnl45dbz4gsjgee

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

Daniel B. Limbrick
2012 2012 IEEE Computer Society Annual Symposium on VLSI  
The area-and timing constrained implementations of the ISCAS85 benchmark circuits are compared for error propagation probability in Figures 6.5 and 6 .11.  ...  Error propagation probability average for the selected LgSynth91 benchmark circuits (range: 80-400 cells) separated by area-constrained and timing-constrained implementations.  ... 
doi:10.1109/isvlsi.2012.67 dblp:conf/isvlsi/Limbrick12 fatcat:6lgrqdpl3veipka3od2vcw5iva

An Ultra-Low-Cost Soft Error Protection Scheme Based on the Selection of Critical Variables

Yohan Ko
2021 Electronics  
The exponentially increasing occurrence of soft errors makes the optimization of reliability, performance, hardware area, and power consumption one of the main concerns in modern embedded processors.  ...  Since the design cost of hardware techniques aimed at improving the reliability of microprocessors is quite expensive for resource-constrained embedded systems, software-level fault tolerance mechanisms  ...  The execution time of vulnerability reduction schemes changes the way a program executes on the processor so that it can exploit some inherent error masking effects.  ... 
doi:10.3390/electronics10172101 fatcat:2hvrsnnpxrgbtb2tms6uu4mkp4

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience [chapter]

Andreas Herkersdorf, Michael Engel, Michael Glaß, Jörg Henkel, Veit B. Kleeberger, Johannes M. Kühn, Peter Marwedel, Daniel Mueller-Gritschneder, Sani R. Nassif, Semeen Rehman, Wolfgang Rosenstiel, Ulf Schlichtmann (+4 others)
2020 Embedded Systems  
be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.  ...  AbstractThe Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron  ...  However, the consequence of layering and specialization for overall system optimization is that such optimizations are typically constrained by the individual layer boundaries.  ... 
doi:10.1007/978-3-030-52017-5_1 fatcat:ip3awa6v6bfrbbciabmtwuxl7a

Improving testability and soft-error resilience through retiming

Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing masking.  ...  Most prior methods of reducing the soft-error rate (SER) involve combinational redesign, which tends to add area and decrease testability, the latter a concern due to the prevalence of manufacturing defects  ...  The proposed techniques exploit certain relationships between observability, testability and SER, and incorporate them into linear programs for retiming optimization.  ... 
doi:10.1145/1629911.1630043 dblp:conf/dac/KrishnaswamyMH09 fatcat:w455dgstlza5xfcqc24jkujivm

On the Reliability Assessment of Artificial Neural Networks Running on AI-Oriented MPSoCs

Annachiara Ruospo, Ernesto Sanchez
2021 Applied Sciences  
This reliability-oriented methodology exploits an integer linear programming solver to find the optimal solution.  ...  Frequently, they are considered intrinsically robust and fault tolerant for being brain-inspired and redundant computing models.  ...  Indeed, depending on the criteria defining the problem, an optimal scheduling solution can be provided by exploiting, for example, integer linear programming.  ... 
doi:10.3390/app11146455 fatcat:mt33qfzudncw5khkqfbi7gje3u

Fault-Tolerant Computing with Heterogeneous Hardening Modes [chapter]

Florian Kriebel, Faiq Khalid, Bharath Srinivas Prabakaran, Semeen Rehman, Muhammad Shafique
2020 Embedded Systems  
On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as  ...  AbstractFault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead.  ...  We would like to thank Arun Subramaniyan, Duo Sun and Segnon Jean Bruno Ahandagbe for their contributions to parts of the works cited in this chapter.  ... 
doi:10.1007/978-3-030-52017-5_7 fatcat:d3wgo4fcvfcldgmhl2hfido5ee

Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance

Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Joseph Blomstedt, Daniel A. Connors
2007 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)  
As a result, PLR ignores many benign faults that do not propagate to affect program correctness.  ...  A real PLR prototype for running single-threaded applications is presented and evaluated for fault coverage and performance.  ...  Acknowledgments The authors would like to thank the anonymous reviewers, Robert Cohn, Manish Vachharajani, Rahul Saxena, and the rest of the DRACO Architecture Research Group for their insightful comments  ... 
doi:10.1109/dsn.2007.98 dblp:conf/dsn/ShyeMRBC07 fatcat:dvnvx7lt5bekfeeczehfc5xzly

Efficient software checking for fault tolerance

Jing Yu, Maria Jesus Garzaran, Marc Snir
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
Software checking approaches are attractive because they require little hardware modification and can be easily adjusted to fit different reliability and performance requirements.  ...  As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection.  ...  However, for commodity processors which are cost-and energy-constrained, the technology used in these extreme reliable systems may not be suitable.  ... 
doi:10.1109/ipdps.2008.4536435 dblp:conf/ipps/YuGS08 fatcat:thlhlaahefexrhx7wkg6xkurfm

Revisiting Symptom-Based Fault Tolerant Techniques against Soft Errors

Hwisoo So, Moslem Didehban, Yohan Ko, Reiley Jeyapaul, Jongho Kim, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava
2021 Electronics  
are actually benign faults by program-level masking effects.  ...  Aggressive technology scaling and near-threshold computing have made soft error reliability one of the leading design considerations in modern embedded microprocessors.  ...  Because several software-level masking effects prevent error propagation from the architectural state to the final output of the program, it is possible  ... 
doi:10.3390/electronics10233028 fatcat:6xmgwau25bgxpjm2jdhjop623y

Design and architectures for dependable embedded systems

Jörg Henkel, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Tahoori, Lars Bauer (+10 others)
2011 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11  
In addition, we present a new classification on faults, errors, and failures.  ...  The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years.  ...  Furthermore, we would like to thank Philip Axer (TU Braunschweig), Thomas Ebi (KIT), and Holm Rauchfuss (TUM) for support in preparing this paper.  ... 
doi:10.1145/2039370.2039384 dblp:conf/codes/HenkelBBBBCEEHHHKLMPRSSTTWW11 fatcat:jrd25bf65nfjxbuuuvy3bz6zsm

Automated Algorithmic Error Resilience for Structured Grid Problems Based on Outlier Detection

Amoghavarsha Suresh, John Sartori
2014 Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization - CGO '14  
As such, we can make use of well-established, statistically rigorous techniques for outlier detection to effectively and efficiently detect errors, and subsequently correct them.  ...  Average overhead is as low as 4.5% for error-resilient iterative structured grid algorithms that tolerate error rates up to 10E-3 and achieve the same output quality as their error-free counterparts.  ...  Certain fault distributions, such as bimodal faults, can result in two faults of nearly equal and opposite magnitudes masking in a coarse-level metric (e.g., L1 block).  ... 
doi:10.1145/2581122.2544140 fatcat:6zfur6uspffffowslbumpomwbe

Approximate Triple Modular Redundancy: A Survey

Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee
2020 IEEE Access  
In contrast, PI expansion/reduction exploited the list of literal-sorted candidates for optimization, and input vulnerability was explored as an optimization approach.  ...  Note that some of the approximation methods are implementable on more than one level. Circuit and hardware level techniques exploit voltage scaling and use inexact or fault hardware.  ...  Unate functions governed by testability [13] Hardware Yes Yes No Yes Transistor topology and input permutations [14] Hardware Hardware n/a Yes n/a n/a  ... 
doi:10.1109/access.2020.3012673 fatcat:annw3bcktfbrdetlwhyv7te6wy

The Art and Science of Integrated System Design

L. Carloni, F. De Bernardinis, A. Sangiovanni Vincencentelli, M. Sgroi
2002 32nd European Solid-State Device Research Conference  
We discuss the importance of carefully defining the platform layers and formally deriving the transitions from one platform to the next, including the role of top-down constraint propagation and bottom-up  ...  foundations and guarantee correctness either by construction or by a set of powerful synthesis and verification tools.  ...  For computer programs, the use of high-level programming languages has replaced for the most part assembly languages; for integrated circuits, regular structures such as gate arrays and standard cells  ... 
doi:10.1109/essderc.2002.194867 fatcat:g2mv45325jdyhoik2bmb763lua

Flexible Hardware Acceleration for Instruction-Grain Lifeguards

Shimin Chen, Michael Kozuch, Phillip B. Gibbons, Michael Ryan, Theodoros Strigkos, Todd C. Mowry, Olatunji Ruwase, Evangelos Vlachos, Babak Falsafi, Vijaya Ramachandran
2009 IEEE Micro  
We thank Anastassia Ailamaki, Limor Fix, Greg Ganger, Michelle Goodstein, Bin Lin, and Radu Teodorescu for their contributions to the LBA project.  ...  Acknowledgments Grants from the US National Science Foundation and from Intel supported this work. Ramachandran is supported in part by NSF grant CCF-0514876.  ...  For all practical purposes, unary propagation provides good support for detecting such exploits.  ... 
doi:10.1109/mm.2009.6 fatcat:apesvolhqzbbtn2rs7ff3g533q
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