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Exploiting Loop-Array Dependencies to Accelerate the Design Space Exploration with High Level Synthesis

Nam Khanh Pham, Amit Kumar Singh, Akash Kumar, Mi Mi Aung Khin
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015   unpublished
To fill such a gap, we explore the structure of the design space by analyzing the dependencies between loops and arrays.  ...  Recently, the requirement of shortened design cycles has led to rapid development of High Level Synthesis (HLS) tools that convert system level descriptions in a high level language into efficient hardware  ...  Vivado HLS tool is used as the High Level Synthesis Tool with Zedboard as the synthesized platform.  ... 
doi:10.7873/date.2015.0199 fatcat:6obkdc34fza5tetbhxw3hjrhea

Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

Brandon Reagen, Yakun Sophia Shao, Gu-Yeon Wei, David Brooks
2013 International Symposium on Low Power Electronics and Design (ISLPED)  
The exploration presented in this work shows that the space is full of poor design choices.  ...  This thorough, detailed design space search of hardware accelerators gives architects a quantitative way to reason about the differences in implementations.  ...  We would like to thank Glenn Holloway for his help revising this work and the anonymous reviewers for their feedback.  ... 
doi:10.1109/islped.2013.6629329 dblp:conf/islped/ReagenSWB13 fatcat:buz5aqyipjhkxbhbya7yrq7wu4

Using estimates from behavioral synthesis tools in compiler-directed design space exploration

Byoungro So, Pedro C. Diniz, Mary W. Hall
2003 Proceedings of the 40th conference on Design automation - DAC '03  
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration.  ...  parallelizing compiler technology and high-level synthesis tools.  ...  In their work, there is no notion of a search algorithm and no interaction with high-level synthesis.  ... 
doi:10.1145/775832.775963 dblp:conf/dac/SoDH03 fatcat:fp2qmdpqsjfylkkwzemjjesebu

Using estimates from behavioral synthesis tools in compiler-directed design space exploration

Byoungro So, Pedro C. Diniz, Mary W. Hall
2003 Proceedings of the 40th conference on Design automation - DAC '03  
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration.  ...  parallelizing compiler technology and high-level synthesis tools.  ...  In their work, there is no notion of a search algorithm and no interaction with high-level synthesis.  ... 
doi:10.1145/775959.775963 fatcat:gd5nzjex4ngh7lbl77y7ci2tfq

ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation [article]

Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen
2021 arXiv   pre-print
High-level synthesis (HLS) has been widely adopted as it significantly improves the hardware design productivity and enables efficient design space exploration (DSE).  ...  ScaleHLS represents HLS designs at multiple representation levels and provides an HLS-dedicated analysis and transform library to solve the optimization problems at the suitable levels.  ...  INTRODUCTION High-level synthesis (HLS) automatically translates highlevel languages into dedicated hardware accelerators, thereby removing the reliance of the cumbersome and potentially error-prone hardware  ... 
arXiv:2107.11673v4 fatcat:rjd3yv7c6zbi7kcqxjp5salv3q

A Survey on System-Level Design of Neural Network Accelerators

Kenshu Seto
2021 Journal of Integrated Circuits and Systems  
We also explain memory optimizations that are effective with the loop optimizations.  ...  Optimizations for CNN models are briefly explained, followed by the recent trends and future directions of the CNN accelerator design.  ...  Since these optimizations are applied to the loop nests of CONV layers, they are especially useful when designing CNN accelerators with high-level synthesis (HLS).  ... 
doi:10.29292/jics.v16i2.505 fatcat:ibbkeob42jepbguezlptws2qha

Automatic generation of efficient accelerators for reconfigurable hardware

David Koeplinger, Christina Delimitrou, Raghu Prabhakar, Christos Kozyrakis, Yaqi Zhang, Kunle Olukotun
2016 SIGARCH Computer Architecture News  
We use our estimation capabilities to rapidly explore a large space of designs across tile sizes, parallelization factors, and optional coarse-grained pipelining, all at multiple loop levels.  ...  However, current tools for targeting FPGAs offer inadequate support for high-level programming, resource estimation, and rapid and automatic design space exploration.  ...  ACKNOWLEDGMENTS The authors thank Maxeler Technologies for their assistance with this paper, and the reviewers for their suggestions.  ... 
doi:10.1145/3007787.3001150 fatcat:e3tcrg2nr5bsbccayasppnkvzm

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

David Koeplinger, Raghu Prabhakar, Yaqi Zhang, Christina Delimitrou, Christos Kozyrakis, Kunle Olukotun
2016 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)  
We use our estimation capabilities to rapidly explore a large space of designs across tile sizes, parallelization factors, and optional coarse-grained pipelining, all at multiple loop levels.  ...  However, current tools for targeting FPGAs offer inadequate support for high-level programming, resource estimation, and rapid and automatic design space exploration.  ...  ACKNOWLEDGMENTS The authors thank Maxeler Technologies for their assistance with this paper, and the reviewers for their suggestions.  ... 
doi:10.1109/isca.2016.20 dblp:conf/isca/KoeplingerPZDKO16 fatcat:wxo2ezckinb37lgkyek2lt4c2q

Software defined architectures for data analytics

Vito Giovanni Castellana, Marco Minutoli, Antonino Tumeo, Marco Lattuada, Pietro Fezzardi, Fabrizio Ferrandi
2019 Proceedings of the 24th Asia and South Pacific Design Automation Conference on - ASPDAC '19  
To reach the levels of efficiency required to process these workflows in real time, upcoming architectures will need to leverage even more workload specialization.  ...  However, their fine-grained nature still leads to issues for the design software and still makes dynamic reconfiguration impractical.  ...  These needs to be integrated in a Design Space Exploration and Synthesis (DSES) engine that leverages the information provided by the high-level abstractions and supports appropriate representations.  ... 
doi:10.1145/3287624.3288754 dblp:conf/aspdac/CastellanaMTLFF19 fatcat:ip4n6z5ghzdubmzs7g6vsq3jmu

Streamroller:

Manjunath Kudlur, Kevin Fan, Scott Mahlke
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to  ...  An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline  ...  The accelerator is designed to exploit the high degree of parallelism available in modulo scheduled loops with a large number of function units (FUs).  ... 
doi:10.1145/1176254.1176321 dblp:conf/codes/KudlurFM06 fatcat:vmp5unqqevcurkdjdkvfxwqeui

Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis [article]

Mang Yu, Sitao Huang, Deming Chen
2022 arXiv   pre-print
Therefore, high-level synthesis (HLS) tools were created to simplify hardware designs for FPGAs.  ...  Conventionally, these accelerators are designed with low-level hardware descriptive languages, which means creating large designs with complex behavior is extremely difficult.  ...  In the light of these demands, the high-level synthesis (HLS) tools are developed to enable designers to describe hardware designs directly using high-level languages, which can significantly reduce the  ... 
arXiv:2207.07917v1 fatcat:fyobfx4osbd4dc6xd6xsrhshwe

Hardware Compilation of Deep Neural Networks: An Overview

Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2018 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
Rather than manually exploring this design space, it is more effective to automate optimisation throughout an end-to-end compilation process.  ...  Deploying a deep neural network model on a reconfigurable platform, such as an FPGA, is challenging due to the enormous design spaces of both network models and hardware design.  ...  In some literature, the authors aimed to design templates with high scalability and flexibility [12] , [36] - [40] , while others applied them within design space explorations to maximise performance  ... 
doi:10.1109/asap.2018.8445088 dblp:conf/asap/ZhaoLNWDNWSCCL18 fatcat:v5txrrsfifa6bah2oksjdlrsgi

Multilevel Granularity Parallelism Synthesis on FPGAs

Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-Mei W. Hwu, Jason Cong
2011 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines  
Evaluation of the rich design space through the full implementation flow -starting with high level source code and ending with routed netlist -is prohibitive in various scientific and computing domains  ...  Recent progress in High-Level Synthesis (HLS) techniques has helped raise the abstraction level of FPGA programming.  ...  ACKNOWLEDGMENT This work is partially supported by the Gigascale Systems Research Center (GSRC) and the Advanced Digital Sciences Center (ADSC) under a grant from the Agency for Science, Technology and  ... 
doi:10.1109/fccm.2011.29 dblp:conf/fccm/PapakonstantinouLSGCHC11 fatcat:krlcxo36ebeojfy7neqtu642kq

Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)

René Cumplido, Peter Athanas, Jürgen Becker
2013 International Journal of Reconfigurable Computing  
We would like to thank all the reviewers for their valuable time and effort in the review process, and to provide constructive feedbacks to authors.  ...  We thank all the authors who contributed to this special issue for submitting their papers and sharing their latest research results.  ...  In "high-level design space and flexibility exploration for adaptive, energy-efficient WCDMA channel estimation architectures, " Z. E.  ... 
doi:10.1155/2013/597323 fatcat:l3v7jtnc5fcsthqi7zluutdnqa

Efficient synthesis of graph methods

Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi
2016 Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16  
We conclude our study by exploring the design space to achieve maximum memory channels utilization.  ...  In this paper, we present a novel architecture to improve the synthesis of graph methods.  ...  High-Level Synthesis (HLS) approaches provide a way to quickly generate hardware descriptions from high-level languages, but current HLS tools are effective in generating serial or parallel accelerators  ... 
doi:10.1145/2966986.2967030 dblp:conf/iccad/MinutoliCTLF16 fatcat:2riiizhprbha3knooihwlvquqm
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