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Exploiting high-level coherence information to optimize distributed shared state
2003
Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03
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In this paper, we focus on application-specific optimizations that exploit dynamic high-level information about an application's spatial data access patterns and the stringency of its coherence requirements ...
InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating systems, and programming ...
In the current work we focus on exploiting application-level coherence information to optimize performance. ...
doi:10.1145/781515.781518
fatcat:w5r5a5ysmjbidmptymqw7zjdzy
Exploiting high-level coherence information to optimize distributed shared state
2003
SIGPLAN notices
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2003; you can also visit the original URL.
The file type is application/pdf.
In this paper, we focus on application-specific optimizations that exploit dynamic high-level information about an application's spatial data access patterns and the stringency of its coherence requirements ...
InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating systems, and programming ...
In the current work we focus on exploiting application-level coherence information to optimize performance. ...
doi:10.1145/966049.781518
fatcat:sp27diwpdvaztm556ktilvq2xm
Exploiting high-level coherence information to optimize distributed shared state
2003
Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2003; you can also visit the original URL.
The file type is application/pdf.
In this paper, we focus on application-specific optimizations that exploit dynamic high-level information about an application's spatial data access patterns and the stringency of its coherence requirements ...
InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating systems, and programming ...
In the current work we focus on exploiting application-level coherence information to optimize performance. ...
doi:10.1145/781498.781518
dblp:conf/ppopp/ChenTSDS03
fatcat:vl2jfzgdurcmrdfa4c7hruaiky
Toward a Model for Shared Data Abstraction with Performance
1998
Journal of Parallel and Distributed Computing
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Access to data shared by concurrent processes is expressed through operations of shared abstract data types (SADTs). SADTs abstract low-level concerns of communication and synchronization. ...
This paper demonstrates the utility of typed shared data abstractions as an effective high-level means of structuring and coordinating parallel programs. ...
The approach delivers both a high level of abstraction to the application developer and simultaneously allows high and scalable performance to be obtained by exploiting the available optimization routes ...
doi:10.1006/jpdc.1998.1427
fatcat:tdsce6iy2zglbnibewt43f6dn4
Design and performance of the Shasta distributed shared memory protocol
1997
Proceedings of the 11th international conference on Supercomputing - ICS '97
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Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals. ...
The long-term goal of WRL is to aid and accelerate the development of high-performance uni-and multi-processors. ...
Therefore, the basic cache coherence protocol in Shasta more closely resembles that of a hardware distributed shared memory system. ...
doi:10.1145/263580.263643
dblp:conf/ics/ScalesG97
fatcat:g5mslgj7ovgsdkaiqgkrpldhdi
Hardware Prediction for Data Coherency of Scientific Codes on DSM
2000
ACM/IEEE SC 2000 Conference (SC'00)
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Once a stream is detected at a loop level, regularity of data access can be exploited at the loop level (spatial locality) but also between loops (temporal locality). ...
A first phase aims at detecting, in the address space regular patterns (called streams) of coherency events (such as requests for exclusive, shared or invalidation). ...
These requests downgrade the coherency state from exclusive to shared, send a copy to the requesting node and to the home node. ...
doi:10.1109/sc.2000.10037
dblp:conf/sc/AcquavivaJ00
fatcat:qzsqb3s2uvc4zic63zpdrjtel4
A Task-Centric Memory Model for Scalable Accelerator Architectures
2010
IEEE Micro
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The Cooperative Shared Memory model 17 is similar to Rigel; it relies on software to properly label shared accesses for performance and achieves scalable performance using a reducedcomplexity hardware ...
We thank the Trusted ILLIAC Center at the Information Trust Institute for their generous contribution of use of their computing cluster to help us complete our research. ...
Doing so allows for data that would otherwise have to exist in the globally coherent state, thus suffering high latency to access the furthest hierarchy level, to be effectively privatized to more local ...
doi:10.1109/mm.2010.6
fatcat:wzxeuc4yrvajbg7jv4jatdagya
Architectural Support and Mechanisms for Object Caching in Dynamic Multithreaded Computations
1999
Journal of Parallel and Distributed Computing
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View caching protocols are more tolerant to responsiveness and occupancy delays and are able to exploit even lower-level responsive communication primitives (such as non-atomic remote memory accesses) ...
A detailed performance analysis of four irregular applications, using the Illinois Concert System on the Cray T3D and the SGI Origin 2000, finds that existing software distributed shared memory (DSM) systems ...
Acknowledgements The authors would like to acknowledge John Plevyak, Julian Dolby, Xingbin Zhang, Scott Pakin, and other members of the Concurrent Systems Architecture Group for their work on various parts ...
doi:10.1006/jpdc.1999.1555
fatcat:hz4xyy3kdfc2jc3lg5tyfmytbq
Optimizing communication in HPF programs on fine-grain distributed shared memory
1997
SIGPLAN notices
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This paper demonstrates that cooperation between a compiler and a memory coherence protocol can improve the performance of High Performance Fortran (HPF) programs running on a fine-grain distributed shared ...
In many programs, however, compile-time information about data accesses would permit data to be transferred more efficiently-if the underlying shared-memory system offered suitable primitives. ...
to Zhichen Xu for the performance debugging tools; and to Bill Pugh's research group for building and distributing the Omega library. ...
doi:10.1145/263767.263780
fatcat:avaui3xewzhx3c6jswy7tpubqe
Optimizing communication in HPF programs on fine-grain distributed shared memory
1997
Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPOPP '97
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A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
This paper demonstrates that cooperation between a compiler and a memory coherence protocol can improve the performance of High Performance Fortran (HPF) programs running on a fine-grain distributed shared ...
In many programs, however, compile-time information about data accesses would permit data to be transferred more efficiently-if the underlying shared-memory system offered suitable primitives. ...
to Zhichen Xu for the performance debugging tools; and to Bill Pugh's research group for building and distributing the Omega library. ...
doi:10.1145/263764.263780
dblp:conf/ppopp/ChandraL97
fatcat:2gjdy2heazd65kqrq6sogsjgxa
Improving memory utilization in cache coherence directories
1993
IEEE Transactions on Parallel and Distributed Systems
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We present two compiler optimizations that exploit the high-level sharing information available to the compiler to further reduce the size of a tagged directory by allocating pointers only when necessary ...
Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. ...
The authors wish to thank Hoichi Cheong and the anonymous reviewers for their helpful comments and suggestions. ...
doi:10.1109/71.246074
fatcat:ysqrrdxxcrhjrpc5t76bkosr2y
The Wisconsin Wind Tunnel project
1994
SIGARCH Computer Architecture News
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This document lists contributors to the Wisconsin Wind Tunnel Project, gives a brief description of the project, and presents references and abstracts to its principal papers, including how to obtain them ...
Three of the designs support user-level software coherence protocols, enabling application-specific protocol optimizations. ...
This paper describes how to optimize communication in HPF programs on fine-grain distributed shared memory (ftp://ftp.cs.wisc.edu/wwt/ppopp97_hpf.{ps,pdf}).
S. Chandra and J. R. Larus. ...
doi:10.1145/192537.192543
fatcat:rvtgkgeonnba3cdbociaiglrdq
A Task-centric Memory Model for Scalable Accelerator Architectures
2010
IEEE Micro
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We evaluate coherence management policies related to the task-centric memory model and show that the overhead of maintaining a coherent view of memory in software can be minimal. ...
from DRAM into shared caches. ...
The authors thank the Trusted ILLIAC Center at the Information Trust Institute for their contribution of use of their computing cluster. The authors also wish to thank Naveen Neelakantam, Matt R. ...
doi:10.1109/mm.2010.1
fatcat:a7zgs53fmbdv5iz5n7dzsythv4
A Task-Centric Memory Model for Scalable Accelerator Architectures
2009
2009 18th International Conference on Parallel Architectures and Compilation Techniques
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We evaluate coherence management policies related to the task-centric memory model and show that the overhead of maintaining a coherent view of memory in software can be minimal. ...
from DRAM into shared caches. ...
The authors thank the Trusted ILLIAC Center at the Information Trust Institute for their contribution of use of their computing cluster. The authors also wish to thank Naveen Neelakantam, Matt R. ...
doi:10.1109/pact.2009.16
dblp:conf/IEEEpact/KelmJLFP09
fatcat:6jxpwblpprhzrcqf7xmirztkti
Temporal wavelet-based compression for 3D animated models
2007
Computers & graphics
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The proposed algorithm exploits the temporal coherence of the geometry component by using a temporal wavelet filtering. ...
Moreover, simulation results show that our approach is competitive for any kind of animated models, whatever the characteristics (parametrically coherent or not, fine/coarse meshes...), contrary to the ...
Moreover, this allows to exploit the spatial correlation between neighbor vertices, and further reduce the data information needed to represent the LF sequence. ...
doi:10.1016/j.cag.2006.09.009
fatcat:jgdsesmu3jgsnint42gf3jghwq
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