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On the Exploitation of Narrow-Width Values for Improving Register File Reliability

Jie Hu, Shuai Wang, S.G. Ziavras
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Reliability, soft errors, narrow-width value, register file, in-register duplication.  ...  The datapath pipeline is augmented to efficiently incorporate parity encoding and parity checking such that error recovery is seamlessly supported in IRD and the parity checking is overlapped with the  ...  Error Detection and Recovery from Detected Soft Errors Integrated with parity coding, IRD checks the parity bits for both 32-bit halves at the first stage of execution.  ... 
doi:10.1109/tvlsi.2009.2017441 fatcat:ryrga5la2nfplaaafqpvrgf4te

A column parity based fault detection mechanism for FIFO buffers

Isidoros Sideris, Kiamal Pekmestzi
2013 Integration  
A non-zero column parity when the FIFO is empty, constitutes an indication of fault, and this property is exploited for fault detection.  ...  The technique has gains in area, power and critical path delay, at the expense of (1) greater detection latency, due to the need for the FIFO to become empty in order to assert a violation and (2) worse  ...  It allows for low cost error detection, at the expense of greater latency.  ... 
doi:10.1016/j.vlsi.2012.03.004 fatcat:spqnbqctybdtxbxlxmkxi43v5q

PSP-Cache: A low-cost fault-tolerant cache memory architecture

Hamed Farbeh, Seyed Ghassem Miremadi
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
To protect these memories, most of the modern processors employ Error Detection Codes (EDCs) or Error Correction Codes (ECCs).  ...  Cache memories constitute a large fraction of processor chip area and are highly vulnerable to soft errors caused by energetic particles.  ...  Error Correction Codes (ECCs) employed in cache memories are based on Hamming code [10] ; and SEC-DED code, that is capable to correct single bit errors and detect twobit errors, is the most conventional  ... 
doi:10.7873/date.2014.177 dblp:conf/date/FarbehM14 fatcat:5jqzuzug5jgrdob5ux4e2d3cgm

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Meilin Zhang, Paul Ampadu
2014 Journal of Low Power Electronics and Applications  
propose to exploit same adjacent tag bits to increase their resilience to soft error [14] .  ...  In our evaluation, we add zero cycle latency for parity code, one cycle latency for SECDED, two cycle latencies for DECTED, and seven cycle latencies for 4EC5ED [23, 33] .  ... 
doi:10.3390/jlpea4010044 fatcat:qbirix7afffkzk6nrhg7xjqdo4

Cost-effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

Taehyun Kwon, Muhammad Imran, Joon-Sung Yang
2020 IEEE Access  
ECC parity bits are generated based on virtual data bits instead of actual message bits, thus resulting in a reduced number of cells for parity bits.  ...  However, a reduced resistance range in multiple storage levels of MLC PCM, introduces a lot of soft errors because of the resistance drift phenomenon.  ...  base programming latency is the base programming latencies for each level.  ... 
doi:10.1109/access.2020.2974013 fatcat:ujrte4ay5jdupccckx3zldy3ba

Antipodal Detection and Decoding for Large Multi-User MIMO with Reduced Base-Station Antennas

Christopher Husmann, Rahim Tafazolli, Konstantinos Nikitopoulos
2018 2018 IEEE Globecom Workshops (GC Wkshps)  
We show that for 32⇥32, 64-QAM modulated systems, and for packet error rates below 10%, Antipodal detection and decoding requires 9 dB less transmitted power than systems employing soft MMSE or LAS detection  ...  For the same scenario, our Antipodal method achieves practical throughput gains of more than 50% compared to soft MMSE and soft LAS-based methods.  ...  The Authors would like to thank the members of University of Surrey 5GIC ( for their support.  ... 
doi:10.1109/glocomw.2018.8644235 dblp:conf/globecom/HusmannTN18 fatcat:nvs7lbv2kjfyniipwcqovhib5y

Reducing Soft Errors through Operand Width Aware Policies

O. Ergin, O. Unsal, X. Vera, A. Gonzalez
2009 IEEE Transactions on Dependable and Secure Computing  
Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands  ...  On average, techniques that make use of the narrowness of the values can provide 49 percent error detection, 45 percent error correction, or 27 percent error avoidance coverage for single bit upsets in  ...  Chip multiprocessors (CMPs) were also used for error detection and correction [16] . Symptom-based soft error detection was proposed in [46] .  ... 
doi:10.1109/tdsc.2008.18 fatcat:erebinw5pzditp57ad6vplnwjy

A Brief Survey of Non-Residue Based Computational Error Correction [article]

Sriseshan Srikanth, Bobin Deng, Thomas M. Conte
2016 arXiv   pre-print
The idea of computational error correction has been around for over half a century.  ...  While residue codes have shown great promise for this purpose, there have been several orthogonal non-residue based techniques.  ...  [26] propose parity prediction for multi-bit error detection and correction in Galois Field multipliers with over 100% of area overhead. Keren et al.  ... 
arXiv:1611.03099v1 fatcat:s3i6irdazvag5krpiamqac3m4u

UnSync: A Soft Error Resilient Redundant Multicore Architecture

Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee
2011 2011 International Conference on Parallel Processing  
With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems.  ...  In this work, we propose a novel redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during  ...  ACKNOWLEDGMENT This work was partially supported by funding from National Science Foundation grants CCF-0916652, CCF-1055094 (CA-REER), NSF I/UCRC for Embedded Systems (IIP-0856090), Raytheon, Intel, SFAz  ... 
doi:10.1109/icpp.2011.76 dblp:conf/icpp/JeyapaulHRSL11 fatcat:dvvhzeihhjaonepq5dunb2cwdu

Analytical Approach For Decoder Delay Reduction Sec-DEDDAEC Codes Derived From Orthogonal Latin Square Codes

B. Swarupa
2016 International Journal Of Engineering And Computer Science  
Although tremendous progress has done in past years on memory designing but still Radiation-induced soft errors is concerned area in the field of soft memories and the single error correction double error  ...  In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits.  ...  error correction and detection The general drawbacks 3 with these methods are latency and speed.  ... 
doi:10.18535/ijecs/v4i10.22 fatcat:3ag2wrb7fzazzkeotrwrycpneu

Zigzag-HVP: A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access

Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
2006 IPSJ Digital Courier  
Error Correction Code (ECC) is widely used to detect and correct soft errors in VLSI caches. Maintaining ECC on a per-word basis, which is preferable in caches with word-based access, is expensive.  ...  This paper proposes Zigzag-HVP, a cost-effective technique to detect and correct soft errors in such caches. Zigzag-HVP utilizes horizontal-vertical parity (HVP).  ...  This paper proposes Zigzag-HVP -a lowcost technique to detect and correct soft errors for these word-based accessed caches.  ... 
doi:10.2197/ipsjdc.2.748 fatcat:lsofniqq5vddhjsqkbt43chfni

PERFECTORY: A Fault-Tolerant Directory Memory Architecture

Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2010 IEEE transactions on computers  
We also develop an online error recovery scheme that protects the directory memory from soft errors. We call our fault-tolerant directory memory architecture PERFECTORY.  ...  We propose a novel online fault detection and correction scheme to enhance yield and resilience to runtime errors at a small performance cost.  ...  Although the parity bit has a hard error, the original parity value is the same as the error value (1 in this case) and the fault in the parity bit does not affect the soft error detectability.  ... 
doi:10.1109/tc.2009.138 fatcat:fwqmdc6czjgjtmu6xy2ksqwcjq

Memory error compensation techniques for JPEG2000

Yunus Emre, Chaitali Chakrabarti
2010 2010 IEEE Workshop On Signal Processing Systems  
Simulation results show that for high bit error rates ( ), the error control coding techniques are not effective and that the algorithm-specific techniques can improve the PSNR quality of up to 10dB higher  ...  We propose three techniques that exploit the fact that the high frequency subband outputs of the discrete wavelet transform (DWT) have small dynamic range and so errors in the most significant bits can  ...  The proposed ECC schemes are based on single error correction double error detection (SECDED) codes where the stronger codes are derived from the weaker codes to minimize the circuit and power overhead  ... 
doi:10.1109/sips.2010.5624759 fatcat:pxyoxystfzflthejgh6hbpokfi

Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values

I. Burak Karsli, Pedro Reviriego, M. Fatih Balli, Oguz Ergin, J. A. Maestro
2013 IEEE computer architecture letters  
Several techniques have recently been proposed to exploit the unused bits in narrow values to protect them against soft errors.  ...  The results show that the scheme is significantly faster than a parity check and can improve substantially the number of soft errors that are corrected compared to existing techniques.  ...  At the circuit level, the results show that Enhanced Duplication can be implemented with a lower latency than a parity check and enables the correction of soft errors that affect a single bit.  ... 
doi:10.1109/l-ca.2012.6 fatcat:qf7vnvgixbfyzcazstxw2nkvxu

Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology

Riaz Naseer, Rashed Zafar Bhatti, Jeff Draper
2006 The ... Midwest Symposium on Circuits and Systems conference proceedings  
Soft errors are a major reliability concern for today's nanometer technologies.  ...  Single Error Correction (SEC) Hamming code and Triple Modular Redundancy (TMR) provide a high-level mitigation solution for soft errors.  ...  ERROR PROBABILITY ANALYSIS OF SOFT ERROR MITIGATION TECHNIQUES For standard cell based ASIC designs, microarchitectural techniques such as TMR and EDAC codes are a possible solution for soft error mitigation  ... 
doi:10.1109/mwscas.2006.382112 fatcat:abqfeqfhxrg27dimywgsgtsjwy
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