1,001 Hits in 7.6 sec

Exploiting die-to-die thermal coupling in 3D IC placement

Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim
2012 Proceedings of the 49th Annual Design Automation Conference on - DAC '12  
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack.  ...  These methods are employed in a force-directed 3D placement successfully and outperform several state-of-the-art placers published in recent literature.  ...  thermal coupling in 3D ICs in force-directed temperatureaware placement.  ... 
doi:10.1145/2228360.2228495 dblp:conf/dac/AthikulwongsePL12 fatcat:ewj33zvazzcy3aoku2slj3cppe

Physical Design Automation for 3D Chip Stacks

Johann Knechtel, Jens Lienig
2016 Proceedings of the 2016 on International Symposium on Physical Design - ISPD '16  
However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips.  ...  The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality  ...  Thus, the thermal coupling within monolithic stacks is larger and more uniform than for TSV-based 3D ICs. This, in turn, calls for dedicated thermal management [21] .  ... 
doi:10.1145/2872334.2872335 dblp:conf/ispd/KnechtelL16 fatcat:3kigpmhpnjahbow2yptm2cjrzm

Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs

Lingjun Zhu, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, Sung Kyu Lim
2020 Proceedings of the 2020 International Symposium on Physical Design  
Due to the short die-to-die distance and inferior heat dissipation capability, Face-to-Face (F2F) boned 3D ICs are often considered to be vulnerable to electrical and thermal coupling.  ...  Next, we investigate the impacts of the coupling on the delay, power, and noise of F2F 3D ICs, and provide guidelines to mitigate these effects.  ...  3D IC Technology Used in This Work In this paper, we will explore the electrical and thermal coupling effects in F2F 3D ICs.  ... 
doi:10.1145/3372780.3378169 dblp:conf/ispd/ZhuCPSYL20 fatcat:qfle26xdqnaixa7fd65pd6zo5a

Through Silicon Via-Based Grid for Thermal Control in 3D Chips [chapter]

José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici
2009 Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering  
Three-dimensional (3D) integration consists of vertical placement and interconnect of several layers of active circuits.  ...  Several works have addressed the layout optimization of lacement of vias for heat dissipation in ⋆  ...  (through silicon vias, inter-die bonding layers, etc.) on thermal performance of a 3D IC.  ... 
doi:10.1007/978-3-642-04850-0_14 fatcat:7lngrosgc5hofk7usxtcomxega

Through Silicon Via-based Grid for Thermal Control in 3D Chips [chapter]

José L. Ayala, Arvind Sridhar, David Atienza, Yusuf Leblebici
2012 Design Technology for Heterogeneous Embedded Systems  
Three-dimensional (3D) integration consists of vertical placement and interconnect of several layers of active circuits.  ...  Several works have addressed the layout optimization of lacement of vias for heat dissipation in ⋆  ...  (through silicon vias, inter-die bonding layers, etc.) on thermal performance of a 3D IC.  ... 
doi:10.1007/978-94-007-1125-9_14 fatcat:jqdxopodzvhxxmr3fd4pu3mtky

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Johann Knechtel, Ozgur Sinanoglu, Ibrahim (Abe) M. Elfadel, Jens Lienig, Cliff C. N. Sze
2017 IPSJ Transactions on System LSI Design Methodology  
chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.  ...  Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for.  ...  Hence, the thermal coupling within monolithic stacks is larger and more uniform than for TSV-based 3D ICs, which calls for dedicated thermal management [45] .  ... 
doi:10.2197/ipsjtsldm.10.45 fatcat:dytlj3s7ajd4rh73iz7uxom7ou

Design Methodologies and Co-Design Options for Novel 3D Technologies [chapter]

Tilman Horst, Robert Fischbach, Jens Lienig
2020 Zenodo  
Subsequently, we investigate related design methodologies in order to find so far neglected potentials for design optimiza  ...  In this paper, we first give an overview of the most relevant and mature 3D technologies.  ...  Therefore, estimated die dimensions are provided by the 2D flow and dummy dies are created in order to perform an early package-level die placement.  ... 
doi:10.5281/zenodo.3632449 fatcat:cyr3drrzbzgvdfagipqfxk4iaq

Three-dimensional Integrated Circuits: Design, EDA, and Architecture

Guangyu Sun
2011 Foundations and Trends® in Electronic Design Automation  
, which could be further categorized as wafer-to-wafer, die-to-wafer, or die-to-die stacking methods.  ...  These multiple layers are then assembled to build up 3D IC, using bonding technology.  ...  Therefore, a thermal-aware 3D placement tool is needed to fully take advantage of 3D IC technology.  ... 
doi:10.1561/1000000016 fatcat:usmthkco4rfavmnlvvmmgxolcq

On Mitigation of Side-Channel Attacks in 3D ICs

Johann Knechtel, Ozgur Sinanoglu
2017 Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17  
Our key idea is to carefully exploit the specifics of material and structural properties in 3D ICs, thereby decorrelating the thermal behaviour from underlying power and activity patterns.  ...  We address the thermal leakage in 3D ICs early on during floorplanning, along with tailored extensions for power and thermal management.  ...  Our key idea is the following: we exploit the specifics of material and structural properties in 3D ICs, in order to effectively decorrelate thermal patterns from the power and activity patterns.  ... 
doi:10.1145/3061639.3062293 dblp:conf/dac/KnechtelS17 fatcat:6oo6cufnkfcffpwasv6uhtymki

A Review of the Design Challenges for the 3-D on Chip Network Paradigms

Neha Jain, Mayank Patel
2017 International Journal of Computer Applications  
covered by vertical interconnects, problems related to optimally determining tier assignments and the placement of switches in 3D circuits.  ...  The next challenge in front of researchers in the domain of NoC is to use NoC architecture as the backbone of the upcoming generation of 3D chips.  ...  Besides, 2D ICs have larger die size in multiprocessor implementations with difficulty in clock distribution.  ... 
doi:10.5120/ijca2017914875 fatcat:c7wzcnumq5ca3evxthiourc66m

Guidelines on thermal management solutions for modern packaging technologies - a review

A. Fodor, G. Chindris, D. Pitica, R. Jano
2015 2015 IEEE 21st International Symposium for Design and Technology in Electronic Packaging (SIITME)  
the previous one reaches its limits, optimizing thermal transfer in the entire system at chip level, package level, and PCB/assembly level.  ...  The current research gives an overview of latest packaging technology along with required thermal management measures and proposes a consistent methodology of Design for Thermal Management.  ...  The method states that lower semiconductor dies can be cooled by thermally coupling the lower semiconductor dies to a heat sink positioned above the interposer, to an upper semiconductor die, to a heat  ... 
doi:10.1109/siitme.2015.7342292 fatcat:yltnjvgn7beq5fkxglsxwsztge

Thermal characterization of cloud workloads on a power-efficient server-on-chip

Dragomir Milojevic, Sachin Idgunji, Djordje Jevdjic, Emre Ozer, Pejman Lotfi-Kamran, Andreas Panteli, Andreas Prodromou, Chrysostomos Nicopoulos, Damien Hardy, Babak Falsari, Yiannakis Sazeides
2012 2012 IEEE 30th International Conference on Computer Design (ICCD)  
The integration of 3D-stacked Wide I/O DRAM on top of a logic die increases available memory bandwidth by using dense and fast Through-Silicon Vias (TSVs) instead of off-chip IOs, enabling faster data  ...  1 We propose a power-efficient many-core server-onchip system with 3D-stacked Wide I/O DRAM targeting cloud workloads in datacenters.  ...  The power density maps and 3D-IC stack configuration serve as inputs to the Compact Thermal Model [21] to generate the thermal profile for the whole chip.  ... 
doi:10.1109/iccd.2012.6378637 dblp:conf/iccd/MilojevicIJOLPPNHFS12 fatcat:cruk6cs3qbbxlhskdzfhzuv6wq

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth (+11 others)
2015 IEEE transactions on computers  
technology and a two-tier 3D stacking technology using 1.2 μ -diameter, 6 μ -height through-silicon vias (TSVs) and μ -diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores  ...  This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process  ...  His research interests include silicon interposer design and co-analysis, TSV-to-TSV coupling in 3D ICs, and thermal analysis of 3D ICs with integrated voltage regulators.Dong Hyuk Woo received the B.S  ... 
doi:10.1109/tc.2013.192 fatcat:hpo4pdupprhtrozu46wadbpnqq

Design space exploration for 3D architectures

Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein
2006 ACM Journal on Emerging Technologies in Computing Systems  
In this article, we give a brief introduction to 3D integration technology, discuss the EDA design tools that can enable the adoption of 3D ICs, and present the implementation of various microprocessor  ...  As fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques is imperative to explore the design space to 3D microarchitectures.  ...  ACKNOWLEDGMENTS The EDA tool implementation in Section 3 was done by Yuh-fang Tsai and Wei-lun Hung. Much of the circuit analysis in Section 4 was conducted by Kiran Puttaswamy.  ... 
doi:10.1145/1148015.1148016 fatcat:752rniivarf4hn5lmnmrtp2acy

Fast and scalable temperature-driven floorplan design in 3D MPSoCs

Ignacio Arnaldo, Alessandro Vicenzi, Jose L. Ayala, Jose L. Risco, J. Ignacio Hidalgo, Martino Ruggiero, David Atienza
2012 2012 13th Latin American Test Workshop (LATW)  
Temperature-driven floorplaners have been recently proposed to alleviate the thermal problem in 3D multi-processor systems-on-chip (MPSoC).  ...  However, the proposed algorithms fail to provide fast placement of the modules when the complexity and the number of functional units in the stack increases.  ...  Compact and Transient Thermal Model In [17] the authors present a compact and transient thermal model to run fast but accurate thermal simulations of 2D or 3D ICs.  ... 
doi:10.1109/latw.2012.6261245 dblp:conf/latw/ArnaldoVARHRA12 fatcat:hhheq6gu25czng7wvchzbh47xe
« Previous Showing results 1 — 15 out of 1,001 results