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Side-channels beyond the cloud edge: New isolation threats and solutions

Mohammad-Mahdi Bazm, Marc Lacoste, Mario Sudholt, Jean-Marc Menaud
2017 2017 1st Cyber Security in Networking Conference (CSNet)  
Time padding, cache cleansing, dynamic partitioning [32], cache locking and multiplexing cache lines [33] are a number of possible countermeasures.  ...  L3 (Last-Level Cache, LLC) is shared among all cores, having a much larger capacity (MBs) than L1 and L2 (KBs).  ... 
doi:10.1109/csnet.2017.8241986 dblp:conf/csnet/BazmLSM17 fatcat:jwuqts2fxvb7zcgq2lzujfy2ra

SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution Attacks [article]

Bowen Tang, Chenggang Wu, Zhe Wang, Lichen Jia, Pen-Chung Yew, Yueqiang Cheng, Yinqian Zhang, Chenxi Wang, Guoqing Harry Xu
2021 arXiv   pre-print
However, recent studies showed that this kind of techniques could be exploited by attackers to leak secret data via transient execution attacks, such as Spectre.  ...  It dynamically partitions the cache system to isolate speculative data and non-speculative data, which can prevent transient execution from being observed by subsequent execution.  ...  Catalyst [34] adopts Intel's CAT [21] , a hardware-supported way partitioning scheme on the last-level cache, to protect the Xen hypervisor with a low memory overhead.  ... 
arXiv:2107.08367v1 fatcat:3ax63aj3zndoplhjorwu5ly6ti

A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography [article]

Xiaoxuan Lou, Tianwei Zhang, Jun Jiang, Yinqian Zhang
2021 arXiv   pre-print
One popular type of such attacks is the microarchitectural attack, where the adversary exploits the hardware features to break the protection enforced by the operating system and steal the secrets from  ...  Side-channel attacks have become a severe threat to the confidentiality of computer applications and systems.  ...  A cache system is hierarchical and typically consists of three levels. Level 1 (L1) and Level 2 (L2) caches are on-core, while Last Level Caches (LLCs) are off-core.  ... 
arXiv:2103.14244v1 fatcat:u35eyivqbngplfa4qrswfsqqti

Timing Cache Accesses to Eliminate Side Channels in Shared Software [article]

Divya Ojha, Sandhya Dwarkadas
2020 arXiv   pre-print
The solution works at all the cache levels and defends against an attacker process running on another core, same core, or another hyperthread.  ...  This vulnerability is exploited by several known attacks, e.g, evict+reload for recovering an RSA key and Spectre variants for data leaked due to speculative accesses.  ...  We thank Sreepathi Pai for his feedback during early discussions of the ideas in this paper.  ... 
arXiv:2009.14732v1 fatcat:mvh4bqq5wbcftdut7dvsnbuhw4

Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA

Maria Mushtaq, Muhammad Asim Mukhtar, Vianney Lapotre, Muhammad Khurram Bhatti, Guy Gogniat
2020 Information Systems  
It then undertakes a qualitative analysis of secret key retrieval efficiency, complexity, and the features being exploited on target cryptosystems in these attacks.  ...  The paper also discusses the mitigation and detection techniques proposed against such attacks and classifies them based on their effectiveness at various levels in caching hardware and leveraged features  ...  ACKNOWLEDGMENTS This work was partially supported by the Pak-France joint research project e-health.  ... 
doi:10.1016/ fatcat:odegutokz5hrhmwsznlc7px6qm

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware

Qian Ge, Yuval Yarom, David Cock, Gernot Heiser
2016 Journal of Cryptographic Engineering  
We classify types of attacks according to a taxonomy of the shared resources leveraged for such attacks. Moreover, we take a detailed look at attacks used against shared caches.  ...  We survey recent attacks that exploit microarchitectural features in shared hardware, especially as they are relevant for cloud computing.  ...  Liu and Lee [106] suggested that the demand-fetch policy of a cache is a security vulnerability, which can be exploited by reuse-based attacks that leverage previously accessed data in a shared cache  ... 
doi:10.1007/s13389-016-0141-6 fatcat:7fvkr7h54rbl5mx6vrochsgtkm

HybCache: Hybrid Side-Channel-Resilient Caches for Trusted Execution Environments [article]

Ghada Dessouky, Tommaso Frassetto, Ahmad-Reza Sadeghi
2019 arXiv   pre-print
We present a generic mechanism for a flexible and soft partitioning of set-associative caches and propose a hybrid cache architecture, called HybCache.  ...  However, this leaves the cache vulnerable to side-channel attacks, where timing differences in shared cache behavior are exploited to infer information on the victim's execution patterns, ultimately leaking  ...  We also acknowledge the relevant work of Tassneem  ... 
arXiv:1909.09599v1 fatcat:ermtym2zpbdxvbrmtbb3jvrw5m

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core [article]

Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser
2020 arXiv   pre-print
Microarchitectural covert channels exploit changes in execution timing resulting from competing access to limited hardware resources.  ...  Covert channels enable information leakage across security boundaries of the operating system.  ...  Heiser's work was supported by Australian Research Council (ARC) grant DP190103743 and the US Asian Office of Aerospace Research and Development (AOARD).  ... 
arXiv:2005.02193v1 fatcat:klhpkfnisfcpzj2xrgqr43sxky

A Novel Scheduling Framework Leveraging Hardware Cache Partitioning for Cache-Side-Channel Elimination in Clouds [article]

Read Sprabery, Rakesh B. Bobba University of Illinois Urbana-Champaign
2017 arXiv   pre-print
Combining the Intel CAT architecture that enables cache partitioning on the fly with novel scheduling techniques and state cleansing mechanisms, we enable cache-side-channel free computing for Linux-based  ...  containers and virtual machines, in particular, those managed by KVM.  ...  last-level cache, and a mechanism to partition the shared last-level cache.  ... 
arXiv:1708.09538v1 fatcat:f52vtm6zrzatpepmpg5umupmlq

IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications [article]

Hamza Omar, Omer Khan
2020 arXiv   pre-print
MI6 architects strong isolation by statically isolating shared memory state, and purging the microarchitecture state of private core, cache, and TLB resources on every enclave entry and exit.  ...  IRONHIDE improves performance by 2.1x over the MI6 baseline for a set of user and OS interactive applications.  ...  Data replication in last-level cache is disabled to ensure that a memory access to each shared cache slice is made by a single process.  ... 
arXiv:1904.12729v3 fatcat:ennb7wyprjf4zpjqrxwrzxb6qm

Disruptive prefetching

Adi Fuchs, Ruby B. Lee
2015 Proceedings of the 8th ACM International Systems and Storage Conference on - SYSTOR '15  
Unfortunately, the behavior of caches can be exploited by attackers to infer the program's memory access patterns, by carrying out cache-based side-channel attacks, which can leak critical information.  ...  Secure caches that were proposed employ cache partitioning or randomized memory-to-cache mapping techniques to prevent these attacks. Such techniques may add to the complexity of cache designs.  ...  Acknowledgements We thank Fangfei Liu for providing us with valuable input on secure cache designs and side-channel attacks; this input greatly helped us leverage the security aspects of this work.  ... 
doi:10.1145/2757667.2757672 dblp:conf/systor/FuchsL15 fatcat:qhymonwxtvdvxhcvnxipbgngkq

Packet Chasing: Spying on Network Packets over a Cache Side-Channel [article]

Mohammadkazem Taram, Ashish Venkat, Dean Tullsen
2020 arXiv   pre-print
of I/O and CPU requests in the last-level cache.  ...  A spy process can easily probe and discover the exact cache location of each buffer used by the network driver.  ...  This research was supported in part by NSF Grants CNS-1652925 and CNS-1850436, NSF/Intel Foundational Microarchitecture Research Grants CCF-1823444 and CCF-1912608, and DARPA under the agreement number  ... 
arXiv:1909.04841v2 fatcat:rrbv6z7bd5egpbwdhmavaw26ti

Towards a Better Indicator for Cache Timing Channels [article]

Fan Yao, Hongyu Fang, Milos Doroslovacki, Guru Venkataramani
2019 arXiv   pre-print
In this work, we show that cache occupancy, which records the number of cache blocks owned by a specific process, can be leveraged as a stronger indicator for the presence of cache timing channels.  ...  Our experimental results show that cache occupancy patterns cannot be easily obfuscated even by advanced adversaries that successfully evade cache miss-based detection.  ...  We implement a prime+probe covert channel attack on last level cache (L2 cache) similar to those prior works [13] , [21] . We generate 32 sets of addresses for the trojan and spy.  ... 
arXiv:1902.04711v1 fatcat:g2qnhcukyfeqjeanrgasqkqzje

Last-Level Cache Side-Channel Attacks are Practical

Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, Ruby B. Lee
2015 2015 IEEE Symposium on Security and Privacy  
We present an effective implementation of the PRIME+PROBE side-channel attack against the lastlevel cache.  ...  We measure the capacity of the covert channel the attack creates and demonstrate a cross-core, cross-VM attack on multiple versions of GnuPG.  ...  Fine-grained cache partitioning can also be done dynamically using special load and store instructions that can lock a security-critical cache line into the cache, as in the partition-locked cache (PLcache  ... 
doi:10.1109/sp.2015.43 dblp:conf/sp/LiuYGHL15 fatcat:v4wsd47m45gevjt5ddlnkrf2lu

A Compiler Assisted Scheduler for Detecting and Mitigating Cache-Based Side Channel Attacks [article]

Sharjeel Khan, Girish Mururu, Santosh Pande
2020 arXiv   pre-print
the maximum capacity of the last level cache.  ...  Side channel attacks steal secret keys by cleverly leveraging information leakages and can, therefore, break encryption.  ...  This is so since the Biscuit's scheduler leverages these predicted cache footprints to schedule the processes such that the total of the cache footprints of all the processes is less than the last-level  ... 
arXiv:2003.03850v3 fatcat:whoi3azw7zajhelbabdtz4d7bi
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