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Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay

Se-Hyun Yang, M.D. Powell, B. Falsafi, T.N. Vijaykumar
Proceedings Eighth International Symposium on High Performance Computer Architecture  
In this paper, we compare and contrast, for the first time, the proposed design choices for resizable caches, and evaluate the effectiveness of cache resizings in reducing the overall energy-delay in deep-submicron  ...  Recent research advocates using "resizable" caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in the cache's unused sections with minimal  ...  Acknowledgments This research is supported in part by SRC under contract 2000-HJ-768. We would like to thank Yuen Chan and the anonymous reviewers for their useful comments.  ... 
doi:10.1109/hpca.2002.995706 dblp:conf/hpca/YangPFV02 fatcat:xwh4kd3darghdp553nwyvdx7w4

Reducing leakage in a high-performance deep-submicron instruction cache

M. Powell, Se-Hyun Yang, B. Falsafi, K. Roy, N. Vijaykumar
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
At the architecture level, we propose the Dynamically ResIzable i-cache (DRI i-cache), a novel i-cache design that dynamically resizes and adapts to an application's required size.  ...  Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage.  ...  ACKNOWLEDGMENT The authors would like to thank S. Borkar, V. De, A. Keshavarzi, and F. Hamzaoglu for information on leakage trends in cache hierarchies in emerging deep-submicron technologies.  ... 
doi:10.1109/92.920821 fatcat:piifiscifvfifjgv43ylsldooe

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Matteo Monchiero, Ramon Canal, Antonio Gonzalez
2009 2009 International Conference on Parallel Processing  
Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique.  ...  This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches.  ...  In this context, the memory hierarchy design is critical to both performance and power. This paper faces the problem of optimizing leakage energy in the secondary (L2) caches of CMP systems.  ... 
doi:10.1109/icpp.2009.28 dblp:conf/icpp/MonchieroCG09 fatcat:3wllmsscl5bpxdp4xi3nmxmu2i

Designing low-power circuits: practical recipes

L. Benini, G. De Micheli, E. Macii
2001 IEEE Circuits and Systems Magazine  
The purpose of this paper is to summarize, mainly by way of examples,what in our experience are the most trustful approaches to lowpower design.  ...  In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power design; rather, we would like to provide insights a designer can rely upon when power  ...  For deep-submicron processes, P Leakage becomes more important.  ... 
doi:10.1109/7384.928306 fatcat:xm5slwbg5jekpg3pg3mzqruc7e

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
high-performance embedded computing demands in an energy-efficient manner.  ...  We also discuss modern multicore processors that leverage these HPEEC techniques to deliver high performance per watt.  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSERC and the NSF.  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

Circuit and microarchitectural techniques for reducing cache leakage power

Nam Sung Kim, K. Flautner, D. Blaauw, T. Mudge
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
According to our projections, in a 70-nm complementary metal-oxide-semiconductor process, drowsy data caches will be able to reduce the total leakage energy consumed in the caches by 60%-75%.  ...  This behavior can be exploited to cut the leakage power of large data caches by putting the cold cache lines into a state preserving, low-power drowsey mode.  ...  Due to short-channel effects in deep-submicron CMOS processes, leakage current reduces substantially with voltage scaling [8] .  ... 
doi:10.1109/tvlsi.2003.821550 fatcat:jussafxrunfbllcvohtdnksixe

Computer Architecture: Challenges and Opportunities for the Next Decade

T. Agerwala, S. Chatterjee
2005 IEEE Micro  
Our challenge as computer architects is to deliver end-to-end performance growth at historical levels in the presence of technology discontinuities.  ...  Applications To design leadership computer systems, we must thoroughly understand the nature of the workloads that such systems are intended to support.  ...  The industry is beginning to use both approaches to counteract the increasing variability of deep-submicron CMOS. Challenge We face a gap.  ... 
doi:10.1109/mm.2005.45 fatcat:vn4hruzdx5cz7kza7263gbo4pe

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Jeren Samandari-Rad, Richard Hughey
2016 IEEE Access  
and energy-delay-product (EDP) of 64KB 16-nm 6T-SRAM could be reduced by ∼12.5X and ∼33%, respectively, as compared to the existing conventional designs.  ...  In this paper, we extend our previously proposed hybrid analyticalempirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new enhanced version, exVAR-TX, to  ...  VARIATION Systematic and random variations in process, supply voltage, and temperature (P, V, T) are a major challenge to the future of high performance micro-processor design SRAM caches.  ... 
doi:10.1109/access.2016.2521385 fatcat:vowwzjai7jhg3iezcclnpdph3e

Implementing branch-predictor decay using quasi-static memory cells

Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Philip W. Diodato, Stefanos Kaxiras
2004 ACM Transactions on Architecture and Code Optimization (TACO)  
With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors.  ...  For these reasons, it is natural to consider applying decay techniques-already shown to reduce leakage energy for caches-to branch-prediction structures.  ...  Margaret Martonosi and Doug Clark's research on energy-efficient processors is supported in part by NSF ITR grant CCR-0086031.  ... 
doi:10.1145/1011528.1011531 fatcat:d4kzsf5lyvbezpmlf7us445oyy

Benefits of decomposing wide CMOS transistors into minimum-size gates

Hans Kristian Otnes Berge, Snorre Aunet
2009 2009 NORCHIP  
One possible answer may be to exploit a multi-objective optimization (MOO) method. Paper II, III and IV apply MOO to circuit design optimization.  ...  To summarize, the various short and narrow channel effects contribution to a V th shift in deep submicron devices are numerous and relatively complicated.  ... 
doi:10.1109/norchp.2009.5397795 fatcat:rr6gli6uxngtxfzm5zk2t5azfq

Multiple Si layer ICs

Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna C. Saraswat
2000 Proceedings of the 37th conference on Design automation - DAC '00  
A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis.  ...  Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays.  ...  Microprocessor Design In microprocessors and DSP processors, most of the critical paths involve on-chip caches [70] .  ... 
doi:10.1145/337292.337394 dblp:conf/dac/SouriBMS00 fatcat:5w4ly4yharaybi4nztrishl7xa

Power efficient branch prediction through early identification of branch addresses

Chengmo Yang, Alex Orailoglu
2006 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06  
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic branch prediction subsystems  ...  In this paper a low power early branch identification technique which enables the design of extremely power-efficient branch predictors and BTBs is proposed.  ...  INTRODUCTION In the last half a dozen years, increasing sensitivity to power consumption has come to constitute one of the defining challenges of processor architecture design.  ... 
doi:10.1145/1176760.1176782 dblp:conf/cases/YangO06 fatcat:dqid3plw65dnbe6h5y56i3bldm

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

S. Yang, M.D. Powell, B. Falsafi, K. Roy, T.N. Vijaykumar
Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture  
At the architectural level, we propose the Dynamically ResIzable i-cache (DRI i-cache), a novel i-cache design that dynamically resizes and adapts to an application's required size.  ...  Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage.  ...  We would like to thank Shekhar Borkar, Vivek De, Ali Keshavarzi, and Faith Hamzaoglu for information on leakage trends in cache hierarchies in emerging deep-submicron technologies.  ... 
doi:10.1109/hpca.2001.903259 dblp:conf/hpca/YangPFRV01 fatcat:ziy5tybs6zhhdjde2hyntk6igm

Harnessing Adaptivity Analysis for the Automatic Design of Efficient Embedded and HPC Systems

Silvia Lovergine, Fabrizio Ferrandi
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
This trend suggests that HPC systems design techniques can be exploited, at a different abstraction level, by embedded systems designers to address shared issues, and vice versa.  ...  On the other side, high-performance computing systems are designed as massively parallel supercomputers with tens of thousands of processors, usually employed to solve complex, highly parallel scientific  ...  CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction.  ... 
doi:10.1109/ipdpsw.2013.230 dblp:conf/ipps/LovergineF13 fatcat:vpdgybp2gnbmve6wzgscv6hqoa

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
, which is important for deep submicron circuits.  ...  Puttaswamy, "Implementing Caches in a 3D Technology for High Performance Processors", International Conference on Computer Design, pp. 525-532, October 2005. [15] N. Oda et al.  ...  Dr His research interest includes modeling and estimation of process variation in deep submicrometer devices and circuits.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky
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