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Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2011 2011 Design, Automation & Test in Europe  
In our FlexMemory design, super-line prefetching is proposed to boost system performance and promote energy efficiency, which leverages the abundant photonic bandwidth to enlarge the effective data fetch  ...  The resulted data fetching mechanism is quite inefficient in performance and energy saving, and cannot effectively utilize the abundant optical bandwidth in off-chip communication.  ...  According to recent researches on silicon photonic communication, the improvement to off-chip bandwidth brought by photonics is impressive.  ... 
doi:10.1109/date.2011.5763157 dblp:conf/date/WangZHLL11 fatcat:v2d3w7fjxrfhndfnmukxsdiag4

Survey of Microarchitectural Side and Covert Channels, Attacks, and Defenses

Jakub Szefer
2018 Journal of Hardware and Systems Security  
Processor microarchitectural side and covert channel attacks have emerged as some of the most clever attacks, and ones which are difficult to deal with, without impacting system performance.  ...  Instead, only malicious or cooperating spy applications need to be co-located on the same machine as the victim.  ...  Acknowledgements The author would like to thank Bryan Ford and Dmitry Evtyushkin for suggesting recent work to add to this survey.  ... 
doi:10.1007/s41635-018-0046-1 dblp:journals/jhss/Szefer19 fatcat:zttnnct3abfztal47n2evmb62e

SEALing Neural Network Models in Secure Deep Learning Accelerators [article]

Pengfei Zuo, Yu Hua, Ling Liang, Xinfeng Xie, Xing Hu, Yuan Xie
2020 arXiv   pre-print
., being vulnerable to physical access based attacks.  ...  Therefore, memory encryption becomes important for DL accelerators on edge devices to improve the security of NN models.  ...  on the GDDR bus to intercept the data communicated between the DL accelerator chip and the DRAM memory.  ... 
arXiv:2008.03752v1 fatcat:6pocvqe6xncrphtdgsheo2hdhu

Memory encryption

Michael Henson, Stephen Taylor
2014 ACM Computing Surveys  
An alternative approach has been to augment existing hardware with operating system enhancements for manipulating keys, providing improved trust.  ...  Memory encryption has yet to be used at the core of operating system designs to provide confidentiality of code and data.  ...  Although the security of systems employing memory encryption is enhanced, attacks on the devices are still possible by etching away the chip walls with acid to reveal internal bus lines for microprobing  ... 
doi:10.1145/2566673 fatcat:jmnwf76mm5calh5vjqh4ukchju

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors [chapter]

Jonathan Valamehr, Ted Huffmire, Cynthia Irvine, Ryan Kastner, Çetin Kaya Koç, Timothy Levin, Timothy Sherwood
2012 Lecture Notes in Computer Science  
3-D integration presents many new opportunities for architects and embedded systems designers. However, 3-D integration has not yet been explored by the cryptographic hardware community.  ...  Traditionally, crypto coprocessors have been implemented as a separate die or by utilizing one or more cores in a chip multiprocessor.  ...  The security community did not believe these attacks could be applied to general computer systems, but a timing attack on a Web server [12] changed this perspective.  ... 
doi:10.1007/978-3-642-28368-0_24 fatcat:awazjhiszrbl5mnz2225ktl4ra

Architectural support for securing application data in embedded systems

Olga Gelbart, Eugen Leontie, Bhagirath Narahari, Rahul Simha
2008 2008 IEEE International Conference on Electro/Information Technology  
However, several attacks are still possible on EED systems when the adversary gains physical access to the system.  ...  We make use of an on-chip FPGA, an architecture that is now commonly available on many processor chips, to build a secure on-chip hardware component that verifies the integrity of application data at run-time  ...  When a cache miss occurs, the memory management logic (in this the cache controller) issues a read to memory on the bus, after which, following the bus protocol, the memory dumps the contents on the bus  ... 
doi:10.1109/eit.2008.4554261 dblp:conf/eit/GelbartLNS08 fatcat:dvalfepaerdptn4qh72l36enie

Embedded System Confidentiality Protection by Cryptographic Engine Implemented with Composite Field Arithmetic

Weike Wang, Xiang Wang, Pei Du, Yuntong Tian, Xiaobing Zhang, Qiang Hao, Zhun Zhang, Bin Xu, N. Mastorakis, V. Mladenov, A. Bulucea
2018 MATEC Web of Conferences  
Embedded systems are subjecting to various kinds of security threats. Some malicious attacks exploit valid code gadgets to launch destructive actions or to reveal critical details.  ...  We implement the AES engine with composite field arithmetic to reduce the cost of hardware implementation. The proposed architecture is implemented on EP2C70 FPGA chip with OpenRisc 1200 based SoC.  ...  CRA attacks exploit valid code gadgets to launch destructive actions or to reveal critical details.  ... 
doi:10.1051/matecconf/201821002047 fatcat:xdgbblsp75hylpzjojjfqnz7zu

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware

Qian Ge, Yuval Yarom, David Cock, Gernot Heiser
2016 Journal of Cryptographic Engineering  
We classify types of attacks according to a taxonomy of the shared resources leveraged for such attacks. Moreover, we take a detailed look at attacks used against shared caches.  ...  We survey recent attacks that exploit microarchitectural features in shared hardware, especially as they are relevant for cloud computing.  ...  Acknowledgements We would like to thank Toby Murray for his comments and feedback.  ... 
doi:10.1007/s13389-016-0141-6 fatcat:7fvkr7h54rbl5mx6vrochsgtkm

An Off-Chip Attack on Hardware Enclaves via the Memory Bus [article]

Dayeol Lee, Dongha Jung, Ian T. Fang, Chia-Che Tsai, Raluca Ada Popa
2019 arXiv   pre-print
This paper shows how an attacker can break the confidentiality of a hardware enclave with Membuster, an off-chip attack based on snooping the memory bus.  ...  First, DRAM requests are only visible on the memory bus at last-level cache misses.  ...  Jeongseok Son from UC Berkeley also contributed to the early stage of the project.  ... 
arXiv:1912.01701v1 fatcat:nj6kipl65zewtd4tn6x6p6gzse

SoftME: A Software-Based Memory Protection Approach for TEE System to Resist Physical Attacks

Meiyu Zhang, Qianying Zhang, Shijun Zhao, Zhiping Shi, Yong Guan
2019 Security and Communication Networks  
We propose SoftME, an approach that utilizes the on-chip memory space to provide a trusted execution environment for sensitive applications.  ...  The experimental results show that our approach improves the security of the system, and there is no significant increase in system overhead.  ...  On-chip memory communicates with the core via the on-chip bus, so it can resist bus attacks. We use data encryption to protect the security of data transmission and storage off-chip.  ... 
doi:10.1155/2019/8690853 fatcat:3yvmgioczjamtesuo4bajbnup4

DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks [article]

Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, Stefan Mangard
2016 arXiv   pre-print
Third, we show how using the DRAM mappings improves existing attacks and in particular enables practical Rowhammer attacks on DDR4.  ...  Using this mapping, we introduce DRAMA attacks, a novel class of attacks that exploit the DRAM row buffer that is shared, even in multi-processor systems.  ...  Acknowledgments We would like to thank our anonymous reviewers as well as Anders Fogh, Moritz Lipp, and Mark Lanteigne for their valuable comments and suggestions.  ... 
arXiv:1511.08756v4 fatcat:umqzhbsdtvhxpfkdnetzfihsxu

CURE: A Security Architecture with CUstomizable and Resilient Enclaves [article]

Raad Bahmani, Ferdinand Brasser, Ghada Dessouky, Patrick Jauernig, Matthias Klimmek, Ahmad-Reza Sadeghi, Emmanuel Stapf
2020 arXiv   pre-print
Moreover, CURE enables the exclusive assignment of system resources, e.g., peripherals, CPU cores, or cache resources to single enclaves.  ...  Third, their protection against cache side-channel attacks is either an afterthought or impractical, i.e., no fine-grained mapping between cache resources and individual enclaves is provided.  ...  We build a RISC-V System-on-Chip (SoC) using the Rocket Chip generator [4] .  ... 
arXiv:2010.15866v1 fatcat:fggaxnplzrejhiejnqeqpm3c2a

Operating system controlled processor-memory bus encryption

Xi Chen, Robert P. Dick, Alok Choudhary
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Unencrypted data appearing on the processormemory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data.  ...  This technique exploits cache locking or scratchpad memory, features present in many embedded processors, permitting the operating system (OS) virtual memory infrastructure to automatically encrypt data  ...  Although many hardware-based bus encryption techniques assume the secret key is stored in on-chip non-volatile memory, this is not a requirement in our technique. 5) Attacker: We assume attackers belong  ... 
doi:10.1145/1403375.1403657 fatcat:5dlo2mun3fa77phufvfbvuuoqa

Operating System Controlled Processor-Memory Bus Encryption

Xi Chen, Robert P. Dick, Alok Choudhary
2008 2008 Design, Automation and Test in Europe  
Unencrypted data appearing on the processormemory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data.  ...  This technique exploits cache locking or scratchpad memory, features present in many embedded processors, permitting the operating system (OS) virtual memory infrastructure to automatically encrypt data  ...  Although many hardware-based bus encryption techniques assume the secret key is stored in on-chip non-volatile memory, this is not a requirement in our technique. 5) Attacker: We assume attackers belong  ... 
doi:10.1109/date.2008.4484834 dblp:conf/date/ChenDC08 fatcat:mt46rmyfhfdhvgeifpfjefsj34

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems

Zhun Zhang, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu, Jinhui Ma
2021 Micromachines  
In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages  ...  guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks.  ...  Furthermore, the growing demands of embedded systems are pushing System-on-Chip (SoC) towards the dramatic improvements in performance and multiple function; these welcome upswings are inevitably accompanied  ... 
doi:10.3390/mi12050560 pmid:34063441 fatcat:o6e4zpjoure6tcx245jzah6wgq
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