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Experimental prototyping of beyond-CMOS nanowire computing fabrics
2013
2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
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Nanoscale 3D-integrated Application Specific ICs (N 3 ASICs) [1], a computing fabric based on semiconductor nanowire grids, is targeted as a scalable alternative to end-of-theline CMOS. ...
We then present a manufacturing pathway as well as show experimental results demonstrating a proof-of-concept metal-gated junctionless nanowire device and N 3 ASIC tile structure with sub-30nm nanowires ...
ACKNOWLEDGMENT The authors acknowledge support of funding agencies: Center for Hierarchical Manufacturing (CHM, NSF DMI-0531171), NSF (CCF-0508382), FCRP Center on Functional Engineered Nano Architectonics ...
doi:10.1109/nanoarch.2013.6623058
dblp:conf/nanoarch/RahmanNKNM13
fatcat:rcfsmrmsbnflfm6qsyavytakaq
Performance simulation and analysis of a CMOS/nano hybrid nanoprocessor system
2009
Nanotechnology
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This paper provides detailed simulation results and analysis of the prospective performance of hybrid CMOS/nano electronic processor systems based upon the Field-Programmable Nanowire Interconnect (FPNI ...
To evaluate this architecture, a complete design was developed for an FPNI implementation using 90-nm CMOS with 15-nm-wide nanowire interconnects. ...
Robinett of the Hewlett-Packard Corporation, plus Prof. K. K. Likharev of Stony Brook University and Prof. M. R. Stan of the University of Virginia, for their many generous discussions. ...
doi:10.1088/0957-4484/20/16/165203
pmid:19420565
fatcat:r22ieosrovftthv5xdljjqjhhu
Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS
[article]
2014
arXiv
pre-print
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Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century. ...
Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. ...
Experimental Prototyping of Beyond-CMOS Nanowire Computing Table 1 | Benchmarking: 16nm Skybridge vs. 16nm CMOS Skybridge; CLA, Carry Look Ahead Adder. *Active Power, †Leakage Power. Fabrics. ...
arXiv:1404.0607v1
fatcat:do4ib2js3bamrk36534pfoiu3q
Computing with a trillion crummy components
2007
Communications of the ACM
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from prototype circuits we have built) of the devices will be nonfunctioning at manufacturing time. ...
Thus, we see this example as an existence proof that the performance of CMOS technology can be extended well beyond currently extrapolated limits by optimizing the metal interconnect, which is already ...
doi:10.1145/1284621.1284644
fatcat:364udmepmveppdugs7bra3nz2e
Design and defect tolerance beyond CMOS
2008
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08
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It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
of application domains currently employing CMOS circuits. ...
of the Moore's Law by estimated 10 to 15 years beyond the "red brick wall" faced by the evolutionary CMOS circuits [38] . ...
doi:10.1145/1450135.1450187
dblp:conf/codes/HuKLNBW08
fatcat:fdscygyokjelxmlzrrlvomle6u
Single-electron operation of a silicon-CMOS 2x2 quantum dot array with integrated charge sensing
[article]
2020
arXiv
pre-print
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Initial demonstrations of quantum dot formation and spin blockade in CMOS foundry-compatible devices are encouraging, but results are yet to match the control of individual electrons demonstrated in university-fabricated ...
We show here that the charge state of quantum dots formed in a CMOS nanowire device can be sensed by using floating gates to electrostatically couple it to a remote single electron transistor (SET) formed ...
ACKNOWLEDGMENTS We acknowledge support from Silicon Quantum Computing P/L, the Australian Research Council (FL190100167, CE170100012 and LE160100069), the NSW Node of the Australian National Fabrication ...
arXiv:2004.11558v1
fatcat:qoibw5keurfx7omax375hurery
Metrology for the Electrical Characterization of Semiconductor Nanowires
2008
IEEE Transactions on Electron Devices
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We describe two unique approaches to successfully fabricate nanowire devices: one based upon harvesting and positioning nanowires and one based upon the direct growth of nanowires in predefined locations ...
Test structures are fabricated and electronically characterized to probe the fundamental properties of chemical-vapor-deposition-grown silicon nanowires. ...
The authors would also like to thank the NIST Center for Nanoscale Science and Technology's Nanofab Facility for the device fabrication support. ...
doi:10.1109/ted.2008.2005394
fatcat:nh4evvmxcjdw5dyikd4pjslkye
Spintronics for low-power computing
2014
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
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Magnetic memories become the most promising candidate for both low power logic computing and the data storage. ...
However this trend tends to run out of steam in recent technology nodes. ...
ACKNOWLEDGMENTS The authors would like to thank the financial support of G3N-NVCPU, ANR-MARS and ANR-DIPMEM projects. ...
doi:10.7873/date.2014.316
dblp:conf/date/ZhangZKKQZRC14
fatcat:vfqxucz2fjgglkw3ieebaymfsa
Nanoelectronics from the bottom up
[chapter]
2009
Nanoscience and Technology
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Devices based on M/a-Si/c-Si nanowires have several attractive features that go beyond earlier planar M2M devices. ...
Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent ...
doi:10.1142/9789814287005_0014
fatcat:jurp7dszkfflbjv4iv5qlbk5ou
Nanoelectronics from the bottom up
2007
Nature Materials
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Devices based on M/a-Si/c-Si nanowires have several attractive features that go beyond earlier planar M2M devices. ...
Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent ...
doi:10.1038/nmat2028
pmid:17972939
fatcat:ba2btodwjzdfpkhkmbp73j2mcu
Technical Program
2021
2021 IEEE Latin America Electron Devices Conference (LAEDC)
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Voltage MOSFETs and
Experimental Validation
Dielectrics
Influence of Dielectrics and Channel Defects on the Electrical
Performance of p-Channel TFTs for CMOS Applications
Dml
The Dual Mode Logic ...
cell
Fabrication of Nanopores Using the Controlled Dielectric
Breakdown Technique
Focused-electron-beam-
induced deposition
A novel bottom-up approach for the fabrication of nanowire-
based spintronic ...
doi:10.1109/laedc51812.2021.9437946
fatcat:7j6djeusvzg2jiiem7qibbqsg4
Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design
[chapter]
2009
Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Nanotube and Nanowire) /CMOS circuits combine both the advantages of Nano-devices and CMOS technologies; they have thus become the most promising candidates to relax the intrinsic drawbacks of CMOS circuits ...
beyond Moore's law. ...
Nanotube and Memristor) [1] [2] [3] [4] are of great interest to relax the intrinsic drawbacks of CMOS technology and improve furthermore the circuit performances beyond the Moore's law. ...
doi:10.1007/978-3-642-04850-0_16
fatcat:mtph3afeszce3dkqehk6gyxwy4
Address generation for nanowire decoders
2007
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07
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Due to the stochastic output of the nanoscale fabrication, the decoder addresses to select the nanowires must be generated after fabrication. ...
We design the algorithms to generate a required number of the proper addresses. Experimental results confirm the efficiency of our algorithms. ...
INTRODUCTION Nanoelectronics is one of the emerging technologies to enable the fabrication of ultra high density electronic devices beyond the current CMOS technology. ...
doi:10.1145/1228784.1228909
dblp:conf/glvlsi/WangKZ07
fatcat:dnxps66c6zc3bj3w7ea5lvzmfy
Architecting NP-Dynamic Skybridge
2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)
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The ROM stores a set of instructions to be executed and has a total capacity of 16x9bits in this prototype. ...
Compared with the pipelining scheme in Skybridge fabric, the operation frequency of each stage increases and thus the computation throughput is improved. ...
doi:10.1109/nanoarch.2015.7180607
dblp:conf/nanoarch/ShiLRKM15
fatcat:haiassqbp5ce7nmz6n3jb5kp5a
Clocking nanocircuits for nanocomputers and other nanoelectronic systems
2007
2007 IEEE International Symposium on Nanoscale Architectures
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Prospective performance bounds are determined by simulation for a class of all-nanoelectronic clocking circuits. ...
Such nanocircuits could be utilized as on-chip master clocks for stand-alone nanosystems, as local clocks within nanoelectronic computers, or as local oscillators in mixed-signal nanoelectronic applications ...
The second approach has the goal of designing and fabricating nanocomputer systems composed entirely of post-CMOS nanoelectronic devices. ...
doi:10.1109/nanoarch.2007.4400867
dblp:conf/nanoarch/DasB07
fatcat:fvzlv2ae2feufm7uv7vlyl3do4
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