Filters








4,226 Hits in 9.5 sec

Exact analysis of the cache behavior of nested loops

Siddhartha Chatterjee, Erin Parker, Philip J. Hanlon, Alvin R. Lebeck
2001 Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation - PLDI '01  
We develop from first principles an exact model of the behavior of loop nests executing in a memory hierarchy, by using a nontraditional classification of misses that has the key property of composability  ...  We use Presburger formulas to express various kinds of misses as well as the state of the cache at the end of the loop nest.  ...  The theorem enables the analysis of cache misses of a composite program fragment in terms of the cache miss behavior of its parts.  ... 
doi:10.1145/378795.378859 dblp:conf/pldi/ChatterjeePHL01 fatcat:qa7563qzcffd7coutsxyaxopvi

Exact analysis of the cache behavior of nested loops

Siddhartha Chatterjee, Erin Parker, Philip J. Hanlon, Alvin R. Lebeck
2001 SIGPLAN notices  
We use Presburger arithmetic to exactly model the behavior of loop nests executing in a memory hierarchy.  ...  Our formulas can be simplified efficiently to count various kinds of cache misses and to determine the state of the cache at the end of the loop nest.  ...  The cache contains all of array C at the end of the first loop nest, so all of the misses of C in the second loop nest are interior misses.  ... 
doi:10.1145/381694.378859 fatcat:stsdblazffhine37pjdvzzsc5q

Associative caches in formal software timing analysis

Fabian Wolf, Jan Staschulat, Rolf Ernst
2002 Proceedings - Design Automation Conference  
We present an approach that extends instruction and data cache modeling from the granularity of basic blocks to program segments thereby increasing the overall running time analysis precision.  ...  Data flow analysis and local simulation of program segments are combined to safely predict cache line contents for associative caches in software running time analysis.  ...  Nested loops with an embedded MFP require the assumption of several cache misses for every iteration.  ... 
doi:10.1145/514074.514076 fatcat:ovcs5ewbwvgg7poxjy7g26konq

Associative caches in formal software timing analysis

F. Wolf, J. Staschulat, R. Ernst
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
We present an approach that extends instruction and data cache modeling from the granularity of basic blocks to program segments thereby increasing the overall running time analysis precision.  ...  Data flow analysis and local simulation of program segments are combined to safely predict cache line contents for associative caches in software running time analysis.  ...  Nested loops with an embedded MFP require the assumption of several cache misses for every iteration.  ... 
doi:10.1109/dac.2002.1012700 fatcat:i5hzbj3ir5bnrcrozpq53v6zxa

Associative caches in formal software timing analysis

Fabian Wolf, Jan Staschulat, Rolf Ernst
2002 Proceedings - Design Automation Conference  
We present an approach that extends instruction and data cache modeling from the granularity of basic blocks to program segments thereby increasing the overall running time analysis precision.  ...  Data flow analysis and local simulation of program segments are combined to safely predict cache line contents for associative caches in software running time analysis.  ...  Nested loops with an embedded MFP require the assumption of several cache misses for every iteration.  ... 
doi:10.1145/513918.514076 dblp:conf/dac/WolfSE02 fatcat:6ayxv3ytnrb4tc5qdmhbuk2mna

Compiler-directed cache polymorphism

J. S. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, W. Zhang
2002 SIGPLAN notices  
Third, based on our reuse analysis, we present an optimization algorithm to compute the cache con gurations for each nest.  ...  First, we present an approach for analyzing data reuse properties of loop nests. Second, we give algorithms to simulate the footprints of array references in their reuse space.  ...  Thus, the behavior of the loop nests determines both performance and energy behavior of applications.  ... 
doi:10.1145/566225.513858 fatcat:leeljlooenhjbc4dtifdkqtiby

Compiler-directed cache polymorphism

J. S. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, W. Zhang
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
Third, based on our reuse analysis, we present an optimization algorithm to compute the cache con gurations for each nest.  ...  First, we present an approach for analyzing data reuse properties of loop nests. Second, we give algorithms to simulate the footprints of array references in their reuse space.  ...  Thus, the behavior of the loop nests determines both performance and energy behavior of applications.  ... 
doi:10.1145/513856.513858 fatcat:szztf23mgjalzflwtlae2njrly

Compiler-directed cache polymorphism

J. S. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, W. Zhang
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
Third, based on our reuse analysis, we present an optimization algorithm to compute the cache con gurations for each nest.  ...  First, we present an approach for analyzing data reuse properties of loop nests. Second, we give algorithms to simulate the footprints of array references in their reuse space.  ...  Thus, the behavior of the loop nests determines both performance and energy behavior of applications.  ... 
doi:10.1145/513829.513858 dblp:conf/lctrts/HuKVISZ02 fatcat:5zfwocbucvawvgomo7oypqllxu

Avoiding the WCET Overestimation on LRU Instruction Cache

L. C. Aparicio, J. Segarra, C. Rodríguez, J. L. Villarroel, V. Viñals
2008 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications  
The complexity of this problem leads existing analysis methods to compute WCET bounds instead of the exact WCET.  ...  In this work we propose a technique to compute the exact instruction fetch contribution to the WCET (IFC-WCET) in presence of a LRU instruction cache.  ...  The previous results can be directly applied on nested loops.  ... 
doi:10.1109/rtcsa.2008.10 dblp:conf/rtcsa/AparicioSRVV08 fatcat:4httyce42rdshkyihkmhf4mn7u

Data cache locking for higher program predictability

Xavier Vera, Björn Lisper, Jingling Xue
2003 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '03  
In order to get predictable cache behavior, we first lock the cache for those parts of the code where the static analysis fails.  ...  When compared to an algorithm that assumes compulsory misses when the state of the cache is unknown, our approach eliminates all overestimation for the set of benchmarks, giving an exact WCMP of the transformed  ...  The authors thank Ebbe for his infinite patience answering all our questions about how to compute WCET. We also thank Janne and Jan Gustafsson for reviewing previous drafts of this paper.  ... 
doi:10.1145/781027.781062 dblp:conf/sigmetrics/VeraLX03 fatcat:6ewco4td2zfu7jrdcqqbxhdgaq

Data cache locking for higher program predictability

Xavier Vera, Björn Lisper, Jingling Xue
2003 Performance Evaluation Review  
In order to get predictable cache behavior, we first lock the cache for those parts of the code where the static analysis fails.  ...  When compared to an algorithm that assumes compulsory misses when the state of the cache is unknown, our approach eliminates all overestimation for the set of benchmarks, giving an exact WCMP of the transformed  ...  The authors thank Ebbe for his infinite patience answering all our questions about how to compute WCET. We also thank Janne and Jan Gustafsson for reviewing previous drafts of this paper.  ... 
doi:10.1145/885651.781062 fatcat:semuazmgzvgkpipormg7zbbkxu

Data cache locking for higher program predictability

Xavier Vera, Björn Lisper, Jingling Xue
2003 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '03  
In order to get predictable cache behavior, we first lock the cache for those parts of the code where the static analysis fails.  ...  When compared to an algorithm that assumes compulsory misses when the state of the cache is unknown, our approach eliminates all overestimation for the set of benchmarks, giving an exact WCMP of the transformed  ...  The authors thank Ebbe for his infinite patience answering all our questions about how to compute WCET. We also thank Janne and Jan Gustafsson for reviewing previous drafts of this paper.  ... 
doi:10.1145/781061.781062 fatcat:xd5fdqpjrnb2pozvywkppzrgc4

Precise miss analysis for program transformations with caches of arbitrary associativity

Somnath Ghosh, Margaret Martonosi, Sharad Malik
1998 SIGPLAN notices  
The Cache Miss Equation (CME) framework discussed in this paper addresses these issues. We express memory reference and cache conflict behavior in terms of sets of equations.  ...  Furthermore, the lack of a general framework for compiler memory performance analysis makes it impossible to understand the combined effects of several program transformations.  ...  In this paper, we consider each loop nest separately; inter-nest analysis is part of our ongoing research.  ... 
doi:10.1145/291006.291051 fatcat:otkhg6ffrrgrfgt4hglrieu66a

Precise miss analysis for program transformations with caches of arbitrary associativity

Somnath Ghosh, Margaret Martonosi, Sharad Malik
1998 Proceedings of the eighth international conference on Architectural support for programming languages and operating systems - ASPLOS-VIII  
The Cache Miss Equation (CME) framework discussed in this paper addresses these issues. We express memory reference and cache conflict behavior in terms of sets of equations.  ...  Furthermore, the lack of a general framework for compiler memory performance analysis makes it impossible to understand the combined effects of several program transformations.  ...  In this paper, we consider each loop nest separately; inter-nest analysis is part of our ongoing research.  ... 
doi:10.1145/291069.291051 dblp:conf/asplos/GhoshMM98 fatcat:yhle6drdpfahjmval22haubmvm

Precise miss analysis for program transformations with caches of arbitrary associativity

Somnath Ghosh, Margaret Martonosi, Sharad Malik
1998 ACM SIGOPS Operating Systems Review  
The Cache Miss Equation (CME) framework discussed in this paper addresses these issues. We express memory reference and cache conflict behavior in terms of sets of equations.  ...  Furthermore, the lack of a general framework for compiler memory performance analysis makes it impossible to understand the combined effects of several program transformations.  ...  In this paper, we consider each loop nest separately; inter-nest analysis is part of our ongoing research.  ... 
doi:10.1145/384265.291051 fatcat:gnf7wya4brbmvdavhkboxtdie4
« Previous Showing results 1 — 15 out of 4,226 results