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Evicted variables and the interaction of global register allocation and symbolic debugging

Ali-Reza Adl-Tabatabai, Thomas Gross
1993 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '93  
This paper addresses the effects of global register allocation and assignment: a register assigned to a variable V may not be holding V's value at a breakpoint since the register can also be assigned to  ...  A symbolic debugger allows a user to display the values of program variables at a breakpoint. However, problems arise if the program is translated by an optimizing compiler.  ...  The following section discusses the problem of debugging optimized code. Section 3 describes our global register allocation model.  ... 
doi:10.1145/158511.158692 dblp:conf/popl/Adl-TabatabaiG93 fatcat:ms2zyd5cwzd7rjebubmaqlrofi

A Practical, Robust Method for Generating Variable Range Tables [chapter]

Caroline Tice, Susan L. Graham
2001 Lecture Notes in Computer Science  
A debugger for optimized code needs to know all of the locations -both registers and memory addresses -in which a variable resides, and which locations are valid for which portions of the computation.  ...  Because optimizations frequently move variables around (between registers and memory or from one register to another) the compiler must build a table to keep track of this information.  ...  Introduction A correct, accurate symbol table is critical for the interactive source-level debugging of optimized code.  ... 
doi:10.1007/3-540-45306-7_8 fatcat:iqfqabsa7ralfo2kmecbcayto4

CheriABI

Brooks Davis, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Robert N. M. Watson (+9 others)
2019 Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '19  
When the process model, user-kernel interactions, dynamic linking, and memory management are all considered, we observe that simple derivation of architectural capabilities is insufficient to describe  ...  The stronger guarantees of these architectural capabilities must be reconciled with the real-world behavior of operating systems, run-time environments, and applications.  ...  The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S  ... 
doi:10.1145/3297858.3304042 dblp:conf/asplos/DavisWRNMBCCFGJ19 fatcat:teo4qzpjlzh7hk2jm3ui2pjwiy

The efficient handling of guards in the design of RPython's tracing JIT

David Schneider, Carl Friedrich Bolz
2012 Proceedings of the sixth ACM workshop on Virtual machines and intermediate languages - VMIL '12  
In this paper, we perform an empirical analysis of runtime properties of guards. This is used to guide the design of guards in the RPython tracing JIT.  ...  These operations occur frequently in generated traces and therefore it is important to design and implement them carefully to find the right trade-off between deoptimization, memory overhead, and (partly  ...  We thank the PyPy and RPython community for their continuous support and work: Armin Rigo, Antonio Cuni, Maciej Fijałkowski, Samuele Pedroni, and countless others. Any remaining errors are our own.  ... 
doi:10.1145/2414740.2414743 fatcat:6k3zzrljmzby5os6vljhjrsywe

A Retargetable Static Binary Translator for the ARM Architecture

Bor-Yeh Shen, Wei-Chung Hsu, Wuu Yang
2014 ACM Transactions on Architecture and Code Optimization (TACO)  
LLBT also effectively reduced the size of the address mapping table, making SBT a viable solution for embedded systems.  ...  Our experiments based on the EEMBC benchmark suite show that the LLBT-generated code can run more than 6× and 2.3× faster on average than emulation with QEMU and HQEMU, respectively.  ...  In LLBT, we allocate architectural states as LLVM local variables and rely on LLVM's register promotion optimizations to promote local variables to virtual registers and LLVM's global register allocation  ... 
doi:10.1145/2629335 fatcat:shjamrqdifagfdac37d3akqyde

Software-Distributed Shared Memory for Heterogeneous Machines: Design and Use Considerations [article]

Loïc Cudennec
2020 arXiv   pre-print
Distributed shared memory (DSM) allows to implement and deploy applications onto distributed architectures using the convenient shared memory programming model in which a set of tasks are able to allocate  ...  With the development of distributed heterogeneous architectures in both HPC and embedded contexts, there is a renewal of interest for systems such as DSM that ease the programmability of complex hardware  ...  Acknowledgments This work has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 688201.  ... 
arXiv:2009.01507v1 fatcat:rvmjt36nefc6nicbtlkcoyfitq

Logic Bug Detection and Localization Using Symbolic Quick Error Detection [article]

Eshan Singh, David Lin, Clark Barrett, Subhasish Mitra
2017 arXiv   pre-print
validation and debug.  ...  We demonstrate the practicality and effectiveness of Symbolic QED using the OpenSPARC T2, a 500-million-transistor open-source multicore System-on-Chip (SoC) design, and using "difficult" logic bug scenarios  ...  We first declare a global variable CFTSS_V_SIGNATURE that holds the current runtime signatures of the program.  ... 
arXiv:1711.06541v1 fatcat:6wrakhzdnvahlfaamsxlnjuvp4

Rationale for a 3D heterogeneous multi-core processor

Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
There are close interactions among all elements, both in terms of executing the project and in empirically justifying 3D-enabled heterogeneity.  ...  Thus, H3 is illustrative of the multi-disciplinary mission of this conference proceedings, the International Conference on Computer Design. • Product strategy -plug-and-play composition of many HMPs from  ...  Any opinions, findings, and conclusions or recommendations expressed herein are those of the authors and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1109/iccd.2013.6657038 dblp:conf/iccd/RotenbergDFZWCTLDF13 fatcat:fufwfjcjvvhirpruhjlxr32see

Cache line reservation

Ivan Bilicki, Vijay Sundaresan, Daryl Maier, Nikola Grčevski, Željko Žilic
2009 Proceedings of the 2009 Conference of the Center for Advanced Studies on Collaborative Research - CASCON '09  
We discuss what kinds of allocations can benefit from CLR, as well as sources of overhead.  ...  Certain objects are allocated from "reserved" cache lines, so that they do not evict other objects that will be needed later.  ...  The root set consists of things like the global and static variables and all addresses that are currently in the registers and the stack.  ... 
doi:10.1145/1723028.1723056 dblp:conf/cascon/BilickiSMGZ09 fatcat:bpss7gddrnbopdur3ookdsidta

Miniphases: compilation using modular and efficient tree transformations

Dmitry Petrashko, Ondřej Lhoták, Martin Odersky
2017 Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI 2017  
Our performance evaluation indicates that this approach reduces the running time of tree transformations by 35% and shows that this is due to improved cache friendliness.  ...  Such an approach harms modularity, and thus makes it hard to maintain and evolve a compiler over the long term, and makes reasoning about performance harder.  ...  His knowledge was very helpful in understanding the evolution of the Scala 2.0-2.12 codebase. This research was supported by the Natural Sciences and Engineering Research Council of Canada.  ... 
doi:10.1145/3062341.3062346 dblp:conf/pldi/PetrashkoLO17 fatcat:3bfpequ7x5ahxnl5b2egvpywja

Miniphases: compilation using modular and efficient tree transformations

Dmitry Petrashko, Ondřej Lhoták, Martin Odersky
2017 SIGPLAN notices  
Our performance evaluation indicates that this approach reduces the running time of tree transformations by 35% and shows that this is due to improved cache friendliness.  ...  Such an approach harms modularity, and thus makes it hard to maintain and evolve a compiler over the long term, and makes reasoning about performance harder.  ...  His knowledge was very helpful in understanding the evolution of the Scala 2.0-2.12 codebase. This research was supported by the Natural Sciences and Engineering Research Council of Canada.  ... 
doi:10.1145/3140587.3062346 fatcat:gbfbpulqlbgabh4cuspwkymmai

DyC: an expressive annotation-directed dynamic compiler for C

Brian Grant, Markus Mock, Matthai Philipose, Craig Chambers, Susan J. Eggers
2000 Theoretical Computer Science  
Only three annotations were required, but a few other changes to the program had to be made due to DyC's lack of support for static global variables.  ...  Directed by a few declarative user annotations that specify the variables and code on which dynamic compilation should take place, a binding-time analysis computes the set of run-time constants at each  ...  work on our dynamic compiler, John O'Donnell and Tryggve Fossum for the source for the Alpha AXP version of the Multiflow compiler, and Ben Cutler, Michael Adler, and Geoff Lowney for technical advice  ... 
doi:10.1016/s0304-3975(00)00051-7 fatcat:tkoaruycxrewza5o6x6mmkuho4

Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems [article]

Dharmesh Tarapore, Shahin Roozkhosh, Steven Brzozowski, Renato Mancuso
2020 arXiv   pre-print
This enduring opacity further obscures the complex interplay among applications and OS-level components, particularly as they compete for the allocation of cache resources.  ...  Notwithstanding the relegation of cache comprehension to proxies such as static cache analysis, performance counter-based profiling, and cache hierarchy simulations, the underpinnings of cache structure  ...  Symbolic Execution is a software technique for feasible path exploration and WCET analysis [10] , [11] of a program subject to variable input vectors.  ... 
arXiv:2007.12271v1 fatcat:y2pxyi7w2rcfzhppupbb3gx7ie

Taming the IXP network processor

Lal George, Matthias Blume
2003 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation - PLDI '03  
Allocation of aggregates: Allocation of aggregates strongly interacts with bank assignment and is difficult to solve heuristically. Therefore, we use ILP to solve the two problems together.  ...  Static single use: Our compiler makes use of a static single use property enforced for certain variables, enabling the register allocator to place these variables into multiple registers at the same time  ...  ACKNOWLEDGEMENTS We thank Satish Chandra for one of the earlier Nova front ends; John Reppy for the control flow graph frequency estimation and as one of the initiators of the Nova project; David Gay for  ... 
doi:10.1145/781132.781135 fatcat:dbumtaujk5fdxoqm7ofifaknqa

Taming the IXP network processor

Lal George, Matthias Blume
2003 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation - PLDI '03  
Allocation of aggregates: Allocation of aggregates strongly interacts with bank assignment and is difficult to solve heuristically. Therefore, we use ILP to solve the two problems together.  ...  Static single use: Our compiler makes use of a static single use property enforced for certain variables, enabling the register allocator to place these variables into multiple registers at the same time  ...  ACKNOWLEDGEMENTS We thank Satish Chandra for one of the earlier Nova front ends; John Reppy for the control flow graph frequency estimation and as one of the initiators of the Nova project; David Gay for  ... 
doi:10.1145/781131.781135 dblp:conf/pldi/GeorgeB03 fatcat:hnhj2lmi3ndjlc5uaiazebgu3m
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