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Transistor-level camouflaged logic locking method for monolithic 3D IC security
2016
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)
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The performance overhead of the proposed method is evaluated with ISCAS'85 benchmark circuits synthesized and placed with a customized M3D IC library. ...
Case study on c6288 benchmark circuit shows that the proposed locking method with the correct key increases the power by only 0.26%. ...
In Section IV, we evaluate our method in terms of output Hamming distance, power consumption profile over time, area overhead, and logic gate delay in several ISCAS'85 benchmark circuits. ...
doi:10.1109/asianhost.2016.7835570
dblp:conf/host/DofeYKSY16
fatcat:ousxx6oa2rcnnjz5zwesexxhwa
On Preventing SAT Attack with Decoy Key-Inputs
2021
2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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Original logic locking proposals provide a high degree of output corruption -i.e., errors on circuit outputsunless it is unlocked with the correct key. ...
Compared with recent related works, SKG-Lock provides higher output corruption, while having high resistance to evaluated attacks. ...
ACKNOWLEDGMENT This work is funded by project MOOSIC ANR-18-CE39-0005 of the French National Research Agency (ANR). ...
doi:10.1109/isvlsi51109.2021.00031
fatcat:sthe2rivlndcnoh6gmuri33me4
Logic Locking Using Hybrid CMOS and Emerging SiNW FETs
2017
Electronics
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We then evaluate the proposed technique based on security metric and performance overhead. ...
The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as ...
Jiann-Shuin Yuan proved the idea, reviewed the manuscript and gave technical feedback. Yu Bi evaluated the performance overhead for the proposed technique and discussed the writing. ...
doi:10.3390/electronics6030069
fatcat:thauh7fsvfcs7duosi4knqesbm
Cyclic Obfuscation for Creating SAT-Unresolvable Circuits
2017
Proceedings of the on Great Lakes Symposium on VLSI 2017 - GLSVLSI '17
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However, the security of both these schemes is called into question by recent SAT based attacks. ...
We demonstrate that cyclic logic locking creates SAT resilient circuits with 40% less area and 20% less delay compared to an insecure XOR/XNOR-obfuscation with the same key length. ...
can be a measure of security. cycle length
3
4
6
8
12
cycle count
area
delay
comp
area
delay
comp
area
delay
comp
area
delay
comp
area
delay
comp
2
12.21
2.88
64
24.59
5.08 ...
doi:10.1145/3060403.3060458
dblp:conf/glvlsi/ShamsiLMZPJ17
fatcat:x3wiqljbqndhnejisxpgrgyuh4
Scaling Logic Locking Schemes to Multi-module Hardware Designs
[chapter]
2020
Lecture Notes in Computer Science
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Logic locking has emerged as a prominent technique to counter these security threats by protecting the integrity of integrated circuits through functional and structural obfuscation. ...
The involvement of third parties in the integrated circuit design and fabrication flow has introduced severe security concerns, including intellectual property piracy, reverse engineering and the insertion ...
Furthermore, we evaluated the cost impact of the approach in terms of area, power and delay overhead compared to various key lengths. ...
doi:10.1007/978-3-030-52794-5_11
fatcat:bb2abv35gngklj466o55vh7ipi
Countermeasure against fault sensitivity analysis based on clock check block
2018
IEICE Electronics Express
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Fault sensitivity analysis (FSA), as a new type of fault attacks, has been proved a serious threat to the security of cryptographic circuits. ...
We first design a clock check block (CCB) to detect the fault clock which is necessary for carrying on FSA, and then design an enable signal module to change the output of the cryptographic circuit once ...
Fault sensitivity analysis (FSA) is a new type of fault attacks, and it has been proved a serious threat to the security of cryptographic circuits. ...
doi:10.1587/elex.15.20180433
fatcat:2gmxpfzkhvf7pfwknp2wn3f5ea
Latch-Based Logic Locking
[article]
2020
arXiv
pre-print
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In this paper, we propose latch-based logic locking, which manipulates both the flow of data and logic in the design. ...
Globalization of IC manufacturing has led to increased security concerns, notably IP theft. ...
This comes at the cost of large delay overheads as the security scales, with an average delay overhead of 60% at their highest security level [10] . ...
arXiv:2005.10649v1
fatcat:s37zppylhfeqhftqotlft3a4iq
Time Transitive Functions for Zero Knowledge Proofs
[article]
2021
arXiv
pre-print
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Continuous verifiable delay functions are an improvement over the basic notion of VDFs with recursive capabilities. ...
Verifiable delay functions have found a lot of applications in blockchain technology in recent times. ...
[3] By architecture designing, evaluation of the input x, runs in parallel time σ(t), on polynomial processors p(t), for the given delay t. ...
arXiv:2108.06389v1
fatcat:dc4hp5hvnbeyloziw3losi6ddu
Microcontroller-based 9 Digits Code Lock System
2019
International Journal of Science and Engineering Applications
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So the system can provide higher level of security than any other system of its kind because longer password length makes the password more secure and the system more powerful in term of security. ...
In this paper, microcontroller-based code lock system which is simple in design, low in cost and high in level of security is presented. ...
The author also thanks to my colleagues in Department of Electronic Engineering, Technological University (Lashio) for their help during developing this system. ...
doi:10.7753/ijsea0807.1015
fatcat:3narujfdfvh2dg3uqpaldmrsvi
ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks
2022
Proceedings of the Great Lakes Symposium on VLSI 2022
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The implementation results show that ENTANGLE can secure large-sized industrial circuits with an average overhead of 11.6 percent and 9.1 percent for area and power, respectively. ...
Among the SAT-resilient logic locking techniques, the Stripped-Functionality-Logic-Locking (SFLL) is the most promising solution which can guard the intellectual property against approximate, sensitization ...
Dummy key: For calculating the area, delay, and power overheads of the Dummy key technique, we locked c7552, b14, and b22 circuits using ENTANGLE and added 1, 4, 8 ,and 16 dummy key bits. ...
doi:10.1145/3526241.3530371
fatcat:zfzct3tlj5cfff6o3ngseenjbm
Remote activation of ICs for piracy prevention and digital right management
2007
Computer-Aided Design (ICCAD), IEEE International Conference on
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The objectives are realized by replication of a few states of the finite state machine (FSM) and adding control to the state transitions. ...
On each chip, the added control signals are a function of the unique IDs and are thus unclonable. ...
The approach is evaluated in terms of delay, power, and area overheads as well as in terms of the achieved security. Fig. 1 . 1 FSM with a lock on the replicated state (S 2 ). ...
doi:10.1109/iccad.2007.4397343
dblp:conf/iccad/AlkabaniKP07
fatcat:k7oimjnkjbfe5kbhaisgpb27se
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA
[article]
2020
arXiv
pre-print
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the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative ...
In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. ...
Similar to the example for private circuits in Sec. II-B, synthesis is unaware of the security notion for locking. ...
arXiv:2001.09672v1
fatcat:72lodqrfhfeanfnatkzkjuoc2i
Active control and digital rights management of integrated circuit IP cores
2008
Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems - CASES '08
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A control structure that coordinates the locking and unlocking of the IPs is embedded within the IC. ...
The IPs can be controlled by the original designer or by the designers who reuse them. Each IP has a built-in functional lock that pertains to the unique unclonable ID of the chip. ...
Experimental evaluations on standard benchmark circuits demonstrate the low overhead and the applicability of the approach on industrial-strength designs. ...
doi:10.1145/1450095.1450129
dblp:conf/cases/AlkabaniK08
fatcat:ne3jelxzgnchjmjnxeahaojcd4
SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection
[article]
2020
arXiv
pre-print
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We evaluate SIGNED on the ISCAS85 and ITC benchmark circuits and obtain a detection accuracy of 87.61\% even for modifications as low as 5-gates. ...
judicious reuse of the locking logic for watermark creation. ...
We observe that SIGNED has negligible impact on the overall area, power and delay of the circuits, meaning that it also successfully satisfies the cost criteria. ...
arXiv:2010.05209v1
fatcat:r4aia6qlxfcr7jxfgskthouqsq
InterLock: An Intercorrelated Logic and Routing Locking
[article]
2020
arXiv
pre-print
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We illustrate that this encoding and BVA-based pre-processing significantly reduces the size of the CNF corresponded to the routing-based obfuscated circuit, in the result of which we observe 100 obfuscation ...
In the CP SAT attack, this is done before subjecting the circuit to the SAT attack. ...
such as delay locking [70] , timing-based locking [16, 38] , or cyclic locking [4, 5, 29, 61, 62] , the obfuscated circuit (I) is not translatable to a SAT problem (delay/timing based), or (II) traps ...
arXiv:2009.02206v1
fatcat:lulv4w35lbgfdjb723aqv4mdom
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