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For the exact same design, with an unchanged interconnect graph and Rent descriptors, as the performance target is raised, more and more wires will need to be promoted to higher performance layers or technologies ...
Therefore, my interest in system-level interconnect prediction is primarily driven by the correlation accuracy as compared to the actual physical routing wires. ...
Rentian models will then allow for very fast estimates for ESL system level architecture exploration and in Networks-on-Chips research for large multicore networks. ...
doi:10.1145/1811100.1811116
dblp:conf/slip/GroeneveldSS10
fatcat:wj535b7m3nhwbkm6tc4kbxq4cm
FIFO power optimization for on-chip networks
2004
Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04
In this context, power (energy) estimation and reduction techniques for switches and links, the core components of an interconnection network, gain added significance. ...
Furthermore, our approach yields increasing energy reduction for wider links that are very likely to be used in future on-chip networks. ...
We studied the traffic characteristics for an onchip network interconnecting the component processors of a distributed shared memory system. ...
doi:10.1145/988952.988998
dblp:conf/glvlsi/BanerjeeD04
fatcat:larhmk5jvzaodozt7ztvrfyzwa
Distributed sensing and cooperative estimation/detection of ubiquitous power internet of things
2019
Protection and Control of Modern Power Systems
Finally, the application prospects of UPIoT and the directions for future research are discussed. ...
The rapid development of Internet Plus Smart Energy requires further strengthening of three kinds of interconnections based on traditional power systems: physical interconnection, information interconnection ...
Finally, the application prospects of UPIoT and directions for future research were discussed. ...
doi:10.1186/s41601-019-0128-2
fatcat:2qtl7zx6ybclfjnofquwzdmapi
PowerHerd
2003
Proceedings of the 17th annual international conference on Supercomputing - ICS '03
Armed with Pow-erHerd, network designers can focus on system performance and power optimization for the average case rather than the worst case, thus making it possible to employ a more powerful interconnection ...
network in the system. ...
Kai Li, for the use of his research group's clusters of workstations at Princeton for our network simulations, and anonymous reviewers for their valuable comments. ...
doi:10.1145/782827.782830
fatcat:loa57yzl6bdrlkzql6q333lyla
Armed with Pow-erHerd, network designers can focus on system performance and power optimization for the average case rather than the worst case, thus making it possible to employ a more powerful interconnection ...
network in the system. ...
Kai Li, for the use of his research group's clusters of workstations at Princeton for our network simulations, and anonymous reviewers for their valuable comments. ...
doi:10.1145/782814.782830
dblp:conf/ics/ShangPJ03
fatcat:636jep2rrzgxjpl7x5zuk22efm
Comparative Study on Load Balancing Algorithm for Multiprocessor Interconnection Networks
2019
International Journal of Advanced Trends in Computer Science and Engineering
The main problem faced in the design of scheduling algorithm is the lack of information about the network load distribution and hence the task execution time estimation. ...
When the demand for computing power increases, Load Balancing problem become important. The purpose of load balancing is to improve the performance of system through an application load. ...
on FCC interconnection network whereas LBSM (STS) performs best for LLB on MC interconnection network. ...
doi:10.30534/ijatcse/2019/13832019
fatcat:bqtkp37htbbb3cvnvyiiycuste
Heterogeneous architecture models for interconnect-motivated system design
2000
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for ...
future architectures. ...
Davis for his homogeneous wirelength models, and P. Zarkesh-Ha for his research in heterogeneous wiring models. ...
doi:10.1109/92.902260
fatcat:pvag4oeoxnbhdd4jfadmschthy
Conclusions and Recommendations for Future Work
[chapter]
2016
Design and Power Quality Improvement of Photovoltaic Power System
and unsymmetrical fault for each component of PV, WES and PV/WES HEPS. 2-Study the digital protection system needed for PV/EU, WES/EU and PV/WES/EU. ...
Conclusions And Suggestions For Future Work 215 12-A computer program for optimal design of a WES to be interconnected with EU accompanied with or with BS has been proposed. ...
doi:10.1007/978-3-319-47464-9_6
fatcat:5sypefkuwvhlrl3ss7ga2jv6iu
PROSPECTS OF RENEWABLE ENERGY RESOURCES AND REGIONAL GRID INTEGRATION FOR FUTURE ENERGY SECURITY & DEVELOPMENT IN SAARC COUNTRIES
2013
International Journal of Research in Engineering and Technology
Investment to Hydro Power and Regional Grid interconnection may be proper step to meet up in a significant amount for future regional energy security in SAARC Countries. ...
Renewable Energy sources (solar, wind, hydro and biomass) are becoming a more important energy option in the future generation systems. ...
For the above reasons, countries are going for interconnection .i.e. the power system interconnection plans have been proposed and are in progress in several regions in Europe, North America, Africa, South-East ...
doi:10.15623/ijret.2013.0201009
fatcat:tk5ccz2nofafbcvbjdhjh7rs3q
Nash-peering: A new techno-economic framework for internet interconnections
2018
IEEE INFOCOM 2018 - IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS)
The current framework of Internet interconnections, based on transit and settlement-free peering relations, has systemic problems that often cause peering disputes. ...
We propose a new techno-economic interconnection framework called Nash-Peering, which is based on the principles of Nash Bargaining in game theory and economics. ...
To estimate B's internal costs, A needs to know the ingress and egress points into B's network for the traffic toward destination D. ...
doi:10.1109/infcomw.2018.8406865
dblp:conf/infocom/ZarchyDDS18
fatcat:j3x24sm6pnerljefz7f74skuqa
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
2006
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)
To assess the potential of on-chip optical interconnects to enhance the performance of future large scale chip multiprocessors. ...
Optical Interconnects have the potential to provide low latency, high bandwidth communication in future large scale Snoop Network -Hierarchical tree • Data Network -Bidirectional ring • Choose 2 snoops ...
Motivation: • Tens or hundreds of cores on-chip in future technologies • Need to provide sufficient data to each core Xu et. al. , Nature, 2005 Ring-resonator based modulator Inverter chain P-I-N diode ...
doi:10.1109/micro.2006.28
dblp:conf/micro/KirmanKDMAWA06
fatcat:ap3wthsaarfxdlt4vcll6b6x54
Embedded Wireless Interconnect for Sensor Networks: Concept and Example
2007
2007 4th IEEE Consumer Communications and Networking Conference
The Open Systems Interconnect (OSI) layered architecture paradigm for computer networks, which led to great successes in wired communications, such as Internet, has been the default paradigm in developing ...
In this paper, we propose the Embedded Wireless Interconnect (EWI), as the potential universal architecture platform for energy stringent wireless sensor and pervasive computing networks, replacing the ...
Moreover, in sensor networks practice, the System layer needs to be at least divided into two parallel sub-layers. ...
doi:10.1109/ccnc.2007.172
dblp:conf/ccnc/SongH07
fatcat:qu3cpyukuvbu3h5zb6h7sqx5ru
North American SynchroPhasor Initiative
2008
Proceedings of the 41st Annual Hawaii International Conference on System Sciences (HICSS 2008)
-Canada Power System Outage Task Force identified the need for such a system as part of their blackout findings [3, 4] . ...
The measurement hardware and associated data networks can then be specified to support these application classes, and future users would understand for example that a network built to Class B specifications ...
doi:10.1109/hicss.2008.328
dblp:conf/hicss/Dagle08
fatcat:3ifyzkbktzanpcd77cnznequbm
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures
[chapter]
2004
Lecture Notes in Computer Science
the on-chip interconnection network. ...
server systems. ...
[12] focused on the need to model power and performance in interconnection networks for multiprocessor design, and they proposed a power model of routers and links. ...
doi:10.1007/978-3-540-30205-6_54
fatcat:d7dail7thbdjhcb3b3dajjuteu
Sliding Banyan network
1996
Journal of Lightwave Technology
Internal packet blocking is efficiently avoided because deflected packets are routed through individualized banyan networks that have "slid" in the time dimension to accommodate each packet's routing needs ...
The Sliding Banyan network is described and evaluated. ...
Section IV contains a discussion of the smart pixel technology needed to implement the SB network and the anticipated performance parameters of a future implementation. ...
doi:10.1109/50.495148
fatcat:oueviwsynjegbdh3bfpxql5eau
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