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Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems [article]

Christian Klarhorst, Martin Flasskamp, Johannes Ax, Thorsten Jungeblut, Wayne Kelly, Mario Porrmann, Ulrich Rückert
2018 arXiv   pre-print
The contribution of our work is an automated framework to estimate the energy consumption at an arbitrary abstraction level without the need to provide further information about the system.  ...  This paper introduces a methodology to develop energy models for the design space exploration of embedded many-core systems. The design process of such systems can benefit from sophisticated models.  ...  Hence, we introduce an energy estimation framework for the CoreVA-MPSoC toolchain.  ... 
arXiv:1801.04242v2 fatcat:en5euxjq45dlfiibghvr7xyr2i

A Signature-Based Power Model for MPSoC on FPGA

Roberta Piscitelli, Andy D. Pimentel
2012 VLSI design (Print)  
This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA.  ...  We integrated the power estimation technique in a system-level MPSoC synthesis framework.  ...  We would like to give special credits to Todor Stefanov and Mohamed Bamakhrama for their support on implementing the MicroBlaze software driver for the PMBus controller.  ... 
doi:10.1155/2012/196984 fatcat:77remrhkjzhk3gjj3y7hiigz5e

Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs

Mohamed M. Sabry, Martino Ruggiero, Pablo G. Del Valle
2010 Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10  
This paper presents a virtual platform for design space exploration of L2 cache architectures in low-power Multi-Processor-Systemson-Chip (MPSoCs).  ...  Cache architectures that work for high performance computers turn out to be inefficient for embedded systems (mainly due to power-efficiency issues).  ...  For completeness and demonstration purposes, we integrated them in an accurate virtual platform environment specifically designed for Embedded MPSoC design space explorations [19] .  ... 
doi:10.1145/1785481.1785552 dblp:conf/glvlsi/SabryRV10 fatcat:whq5r6zfmnhojimxs4q3qm5wwq

Energy-aware synthesis of application specific MPSoCs

Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra, Sri Parameswaran
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
These algorithms are aided by two estimators that can quickly estimate period and energy consumption of a given design point.  ...  Our framework searches for a design with minimum energy consumption under area and period constraints.  ...  [22] targeted runtime adaptation of L1 data cache to minimize energy consumption of a heterogeneous MPSoC architecture. Jung et al.  ... 
doi:10.1109/iccd.2013.6657026 dblp:conf/iccd/MuthukaruppanJMP13 fatcat:ylgsqlpncrevfhe2vm3zgnwqyi

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman Unsal, Adrian Cristal
2014 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)  
The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures.  ...  This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow.  ...  To answer the above challenges, we propose an efficient power/energy estimation tool for consumption estimation of heterogeneous MPSoC platforms.  ... 
doi:10.1109/patmos.2014.6951910 dblp:conf/patmos/RethinagiriPMUC14 fatcat:sfyc7uu4rnfefcau2jwy25wa2i

A method for NoC-based MPSoC energy consumption estimation

Andre L. M. Martins, Douglas R. G. Silva, Guilherme M. Castilhos, Thiago M. Monteiro, Fernando G. Moraes
2014 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)  
This paper presents a method to estimate the energy/power for NoCs and processors from an RTL description, applying the proposed method to an MPSoC (36 processing elements interconnected by a 2D-mesh NoC  ...  State-of-the-art proposals estimate the energy due to the NoC or the processing elements. Few works address the energy modeling and estimation for a NoC-based MPSoCs.  ...  [9] provides a generic model to estimate the power dissipation early in the design flow for MPSoCs. The Authors couple the power models into an architectural simulator.  ... 
doi:10.1109/icecs.2014.7050013 dblp:conf/icecsys/MartinsSCMM14 fatcat:kdobjm2kyncixcfexmumvok7de

A High-Level Power Model for MPSoC on FPGA

R. Piscitelli, A. Pimentel
2012 IEEE computer architecture letters  
We would like to give special credits to Todor Stefanov, and Mohamed Bamakhrama for their support on implementing the Microblaze software driver for the PMBus controller.  ...  More important in the context of early design space exploration, however, is the fact that our power model appears to be very capable of estimating the right power consumption trends for the various MPSoC  ...  An important element of system-level design is the highlevel modeling for architectural power estimation.  ... 
doi:10.1109/l-ca.2011.24 fatcat:mtrb75ltpzbj7dg4u6userknry

Open-People: Open Power and Energy Optimization PLatform and Estimator [chapter]

Daniel Chillet
2011 Lecture Notes in Computer Science  
This paper addresses this problem and proposes a global framework for power/energy estimation and optimization of heterogeneous MultiProcessor System on Chip (MPSoC).  ...  order to reduce energy and power consumption of the system.  ...  From the measurements, the designer can build models and compute an estimation of the energy and/or power consumption of its system.  ... 
doi:10.1007/978-3-642-17752-1_26 fatcat:guxd6j5qcnewrkgju2cjwka3g4

Open-People: Open Power and Energy Optimization PLatform and Estimator

E. Senn, D. Chillet, O. Zendra, C. Belleudy, S.Bilavarn, R. Ben Atitallah, C. Samoyeau, A. Fritsch
2012 2012 15th Euromicro Conference on Digital System Design  
This paper addresses this problem and proposes a global framework for power/energy estimation and optimization of heterogeneous MultiProcessor System on Chip (MPSoC).  ...  order to reduce energy and power consumption of the system.  ...  From the measurements, the designer can build models and compute an estimation of the energy and/or power consumption of its system.  ... 
doi:10.1109/dsd.2012.98 dblp:conf/dsd/SennCZBBASF12 fatcat:nqyx64pysval3lkvwmd6bjpjny

A High-Level Power Model for MPSoC on FPGA

Roberta Piscitelli, Andy D. Pimentel
2011 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum  
We would like to give special credits to Todor Stefanov, and Mohamed Bamakhrama for their support on implementing the Microblaze software driver for the PMBus controller.  ...  More important in the context of early design space exploration, however, is the fact that our power model appears to be very capable of estimating the right power consumption trends for the various MPSoC  ...  An important element of system-level design is the highlevel modeling for architectural power estimation.  ... 
doi:10.1109/ipdps.2011.133 dblp:conf/ipps/PiscitelliP11 fatcat:3sw7nlkbczfm3oqvbf4m5gkjqq

System-level power-performance trade-offs in bus matrix communication architecture synthesis

Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
First, we develop energy macro-models for system-level exploration of bus matrix communication architectures.  ...  First, we develop energy macromodels for system-level exploration of bus matrix communication architectures.  ...  Our work differs from existing work in that we focus on the bus matrix communication architecture, for which we create an automated synthesis framework to enable exploration of power-performance trade-offs  ... 
doi:10.1145/1176254.1176327 dblp:conf/codes/PasrichaPKD06 fatcat:mebbfkajjvdsjfttcpligm2fly

ASAM: Automatic Architecture Synthesis and Application Mapping

Lech Jozwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri (+1 others)
2012 2012 15th Euromicro Conference on Digital System Design  
.  Abstract -This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable applicationspecific instruction-set  ...  Index Terms-embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), customizable ASIPs, architecture synthesis, MPSoC and ASIP design automation;  ...  The selected design points are characterized in terms of timing, area and energy consumption, when exploiting the support for technology awareness described in Section D.  ... 
doi:10.1109/dsd.2012.28 dblp:conf/dsd/JozwiakLCMMMDGJPPTR12 fatcat:et5s2vcnhzbfrae2jufsqzq4gy

Fuzzy logic based energy and throughput aware design space exploration for MPSoCs

Muhammad Yasir Qadri, Nadia N. Qadri, Klaus D. McDonald-Maier
2016 Microprocessors and microsystems  
Therefore there is a need of an adaptive multicore architecture that can be tailored 30 for the application in use for higher energy efficiency.  ...  10 1 2 a r t i c l e i n f o 13 Article history: 14 Available online xxxx 15 Keywords: 16 Design space exploration 17 Multicore processing 18 Fuzzy logic 19 Energy efficiency 20 2 1 a b s t r a c t 22  ...  cache size and associativity play an important role in 545 determining the throughput and energy consumption of an 546 MPSoC.  ... 
doi:10.1016/j.micpro.2015.08.001 fatcat:laqptesczve33msku7aol7yjsu

Hybrid system level power consumption estimation for FPGA-based MPSoC

Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smail Niar, Eric Senn, Jean-Luc Dekeyser
2011 2011 IEEE 29th International Conference on Computer Design (ICCD)  
This paper proposes an efficient Hybrid System Level (HSL) power estimation methodology for FPGA-based MPSoC.  ...  The proposed methodology is also scalable for exploring complex embedded architectures.  ...  To estimate the power consumption of an MPSoC system, the first step is to divide the architecture into different functional blocks and then to cluster the components that are concurrently activated when  ... 
doi:10.1109/iccd.2011.6081403 dblp:conf/iccd/RethinagiriANSD11 fatcat:jmlqz5kybraideblbjbhm5zazm

An Approach for Power Estimation at Electronic System Level using Distributed Simulation

Helder F. A. Oliveira, Alisson V. Brito, Joseana M. F. R. Araujo, Elmar U. K. Melcher
2016 Journal of Integrated Circuits and Systems  
As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used.  ...  The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain  ...  As well as techniques for energy consumption reduction, power consumption estimation in an SoC can be performed at various levels of abstraction.  ... 
doi:10.29292/jics.v11i3.440 fatcat:mqzwykq2yfgezkrn5riop47qtu
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