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Error resynchronization in producer-consumer systems

David L. Russell, Thomas H. Bredt
1975 Proceedings of the fifth symposium on Operating systems principles - SOSP '75  
This paper ~s concerned with error processing for parallel producer-consumer interactions such as encountered in the desing of multi-process operating systems.  ...  Solutions to resynchronization problems that occur when a consumer process detects errors in information received from a producer process are presented.  ...  ACKNOWLEDGEMENTS The authors would like to thank Hector Garcia for the solution presented in Figure 4 .  ... 
doi:10.1145/800213.806528 dblp:conf/sosp/RussellB75 fatcat:bohp5pdtcjgyrp5v5rd2mlqssu

Left ventricular resynchronization in H.F.: Comparison of alternative optimization methods

M. Graziano, C. Valzania, D. Bianchini, G. Loreti, I. Corazza, R. Zannoli
2008 2008 Computers in Cardiology  
compares the results of two different procedures, Doppler Ultrasound and Transthoracic Impedance, to monitor the left ventricular stroke volume on a group of heart failure patients submitted to electrical resynchronization  ...  The two procedures have been applied in parallel on 9 patients by changing the stimulation delays between the septal and posterior ventricular walls and the results have been compared to evaluate the correlation  ...  a very time consuming procedure [2] .  ... 
doi:10.1109/cic.2008.4748995 fatcat:yknr3vn5rvazrebof4kyhamu3u

A Novel Resynchronization Method for Scalable Video Over Wireless Channel

Yu Wang, Lap-pui Chau, Kim-hui Yap
2006 2006 IEEE International Conference on Multimedia and Expo  
markers in different enhancement layer units for reliable transmission of the video over error-prone channels.  ...  A novel resynchronization method is proposed where joint group of picture (GOP) level and picture level insertion of resynchronization marker approach is applied to insert different amount of resynchronization  ...  The more bits consumed by resynchronization markers, the larger the value of the distortion RM D .  ... 
doi:10.1109/icme.2006.262869 dblp:conf/icmcs/WangCY06 fatcat:ifrmfrb7vzb77bodepjnh2owbe

The Signal Passing Interface and Its Application to Embedded Implementation of Smart Camera Applications

S. Saha, S. Puthenpurayil, J. Schlessman, S.S. Bhattacharyya, W. Wolf
2008 Proceedings of the IEEE  
A flexible, optimized communications interface suitable for smart camera systems has been demonstrated in systems for matching facial images and for efficient compression of speech.  ...  ABSTRACT | Embedded smart camera systems comprise computation-and resource-hungry applications implemented on small, complex but resource-hardy platforms.  ...  of tokens that are produced or consumed.  ... 
doi:10.1109/jproc.2008.928744 fatcat:jozhrbcvpbdbloeyqvoqnpe23m

An ECG-on-Chip With 535 nW/Channel Integrated Lossless Data Compressor for Wireless Sensors

Chacko John Deepu, Xiaoyang Zhang, Wen-Sin Liew, David Liang Tai Wong, Yong Lian
2014 IEEE Journal of Solid-State Circuits  
This paper presents a low-power ECG recording system-on-chip (SoC) with on-chip low-complexity lossless ECG compression for data reduction in wireless/ambulatory ECG sensor devices.  ...  Implemented in a standard 0.35 um process, the compressor uses 0.565K gates/channel occupying 0.4 mm2 for four channels, and consumes 535 nW/channel at 2.4 V for ECG sampled at 512 Hz.  ...  SYSTEM ARCHITECTURE OF ECG SOC CHIP The system block diagram of the proposed ECG SoC is shown in Fig. 1 .  ... 
doi:10.1109/jssc.2014.2349994 fatcat:2yzo3qd45rabnn4s47qfjbu6gm

Memory controller policies for DRAM power management

Xiaobo Fan, Carla Ellis, Alvin Lebeck
2001 Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01  
This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems.  ...  The increasing importance of energy e ciency has produced a m ultitude of hardware devices with various power management features.  ...  Acknowledgements This work supported in part by NSF Grants CCR-0082914, EIA-99-72879, EIA-99-86024, NSF CAREER Award MIP-97-02547, Duke University, and equipment donations from Intel and Microsoft.  ... 
doi:10.1145/383082.383118 dblp:conf/islped/FanEL01 fatcat:d7vjlq4ojfbgtfne2pmrq2ttpy

Wireless Video Communications [chapter]

Madhukar Budagavi, Raj Talluri
1999 Electrical Engineering Handbook  
Audio, video, and data processing blocks-These blocks basically produce/consume the multimedia information that is communicated.  ...  These resynchronization words are chosen such that they are unique from the valid video bitstream. That is, no valid combination of the video algorithm's VLC tables can produce these words.  ... 
doi:10.1201/noe0849321672.ch31 fatcat:hha6bfygjbb3xptkaq43zggfj4

Wireless Video Communications [chapter]

Madhukar Budagavi, Raj Talluri
2002 The Communications Handbook  
Audio, video, and data processing blocks-These blocks basically produce/consume the multimedia information that is communicated.  ...  These resynchronization words are chosen such that they are unique from the valid video bitstream. That is, no valid combination of the video algorithm's VLC tables can produce these words.  ... 
doi:10.1201/9781420041163-91 fatcat:qtoj4sdgnvhbdjghvtssunofwu

An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications

Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne Wolf
2008 2008 Design, Automation and Test in Europe  
However, the design of such systems poses various challenges due to the complexities posed by the applications themselves as well as the heterogeneous nature of the targeted platforms.  ...  Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high throughput in a cost-efficient  ...  Acknowledgements This research was supported in part by grant number 0325119 from the U.S. National Science Foundation.  ... 
doi:10.1109/date.2008.4484845 dblp:conf/date/SahaSPBW08 fatcat:33jpzxk6nfd7zntbcqktb4faw4

An optimized message passing framework for parallel implementation of signal processing applications

Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne Wolf
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
However, the design of such systems poses various challenges due to the complexities posed by the applications themselves as well as the heterogeneous nature of the targeted platforms.  ...  Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high throughput in a cost-efficient  ...  Acknowledgements This research was supported in part by grant number 0325119 from the U.S. National Science Foundation.  ... 
doi:10.1145/1403375.1403671 fatcat:balkvrrbw5fptl2j5sr5s626u4

Layered interactive convergence for distributed clock synchronization

Raghukul Tilak, Alan D. George, Robert W. Todd
2002 Microprocessors and microsystems  
However, this approach suffers from limits in terms of system scalability due to resource overhead.  ...  A clock synchronization service ensures that spatially dispersed and heterogeneous processors in a distributed system share a common notion of time.  ...  By contrast, a layered system with the improved precision option consumes about 50% of the CPU resources consumed by the flat ICV.  ... 
doi:10.1016/s0141-9331(02)00066-2 fatcat:vubn3d67nnarvgwiu67xl5dyca

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Davide Zoni, William Fornaciari
2015 ACM Journal on Emerging Technologies in Computing Systems  
To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.  ...  To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating.  ...  Note that the two cycles may have different frequencies (producer verus consumer). In the worstcase, it takes three cycles to deliver the message to the destination.  ... 
doi:10.1145/2751561 fatcat:4rpwdowomfeirif677l2brlaha

Manual Intracardiac Electrogram Method Is Accurate Alternative to Echocardiography for Atrioventricular and Interventricular Optimization in Cardiac Resynchronization Therapy

Borka Pezo Nikolić
2017 Acta Clinica Croatica  
Some manufacturers do not provide automated intracardiac electrogram method (IEGM) systems for atrioventricular (AV) and interventricular (VV) delay optimization in cardiac resynchronization therapy (CRT  ...  It also emphasizes the need for implementation of automated IEGM systems in as many CRT devices as possible.  ...  Sample size was calculated to be 45, when considering type 1 error (a) to be 5% and type 2 error (b) to be 20%. Statistical analyses were performed using STATISTICA, ver. 6.0.  ... 
doi:10.20471/acc.2017.56.04.06 pmid:29590714 fatcat:3v24ujyb7rc3baz57ot67ozetu

Microsecond-Accuracy Time Synchronization Using the IEEE 802.15.4 TSCH Protocol

Atis Elsts, Simon Duquennoy, Xenofon Fafoutis, George Oikonomou, Robert Piechocki, Ian Craddock
2016 2016 IEEE 41st Conference on Local Computer Networks Workshops (LCN Workshops)  
ACKNOWLEDGMENTS This work was performed under the SPHERE (a Sensor Platform for Healthcare in a Residential Environment) Interdisciplinary Research Collaboration (IRC) funded by the UK Engineering and  ...  [2] , however this RTC consumes extremely low-power and is very suitable in order to minimize current draw during deep sleep.  ...  More frequent resynchronization makes the system more robust and quicker to adapt to changes in drift, and in typical settings does not have large impact on energy consumption (Section VI, Fig. 13b ).  ... 
doi:10.1109/lcn.2016.042 dblp:conf/lcn/ElstsDFOPC16 fatcat:ei6vm7s73jfxvpgifkzbnauqdy

Hardware Assisted Clock Synchronization for Real-Time Sensor Networks

Maxim Buevich, Niranjini Rajagopal, Anthony Rowe
2013 2013 IEEE 34th Real-Time Systems Symposium  
This is accomplished through two main hardware sub-systems. First, we improve upon the circuit presented in [1] that synchronizes clocks using the ambient magnetic fields emitted from power lines.  ...  Periodic discrete updates can introduce interpolation errors as compared to continuous update approaches and they require the CPU to expend energy during these wake up periods.  ...  With the fixed periodic approach, the system has to frequently wake up to resynchronize.  ... 
doi:10.1109/rtss.2013.34 dblp:conf/rtss/BuevichRR13 fatcat:j2tfgonrgngy3joy2rmfqnup7i
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