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Equivalence checking for behaviorally synthesized pipelines
2012
Proceedings of the 49th Annual Design Automation Conference on - DAC '12
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We present an equivalence checking approach for certifying synthesized hardware designs in the presence of pipelining transformations. ...
Our approach works by (1) constructing a provably correct pipeline reference model from sequential specification, and (2) applying sequential equivalence checking between this reference model and synthesized ...
We sincerely thank Disha Gandhi, Naren Narasimhan, Jin Yang, and Zhenkun Yang for their help. ...
doi:10.1145/2228360.2228423
dblp:conf/dac/HaoRX12
fatcat:um7xs4vjtvefbngkrbh73jjnvi
Equivalence checking for function pipelining in behavioral synthesis
2014
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
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Sequential equivalence checking (SEC) support is highly desired to provide confidence in the correctness of synthesized pipelines. ...
Furthermore, function pipelines include hardware logic for dynamically inserting "bubbles" (pipeline stalls), which bring additional difficulties in equivalence checking. ...
We thank Yatin Hoskote, Naren Narasimhan, and Jin Yang for their advice and help. ...
doi:10.7873/date.2014.163
dblp:conf/date/HaoRX14
fatcat:l6axsv5oind2hdslaczepykfmm
Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs
[article]
2017
arXiv
pre-print
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Our proposed method enables us to deal with the equivalence checking problem for behaviorally synthesized designs even in the presence of pipelines for nested loops. ...
In this paper, we present an efficient formal approach to check the equivalence of synthesized RTL against the high-level specification in the presence of pipelining transformations. ...
The authors of [14] solved the problem of equivalence checking for function pipelining (instead of loop pipelining) in behavioral synthesis. ...
arXiv:1712.09818v1
fatcat:xfnkdt765nfhvnfnujgs7rscpm
Formal Verification for High-Assurance Behavioral Synthesis
[chapter]
2009
Lecture Notes in Computer Science
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We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. ...
We show how to decompose this certification into two components, which can be respectively handled by the complementary verification techniques, theorem proving and model checking. ...
The transformed CCDFG can then be used for equivalence checking with the synthesized design. ...
doi:10.1007/978-3-642-04761-9_25
fatcat:egb5aum7xvbw3nikyiuz2z2vdi
Optimizing equivalence checking for behavioral synthesis
2010
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
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We present a suite of optimizations for equivalence checking of RTL generated through behavioral synthesis. ...
Experiments on representative benchmarks indicate that the optimizations can handle equivalence checking of synthesized designs with tens of thousands of lines of RTL. ...
In a previous paper [1] , we proposed a framework for certifying behaviorally synthesized RTL. ...
doi:10.1109/date.2010.5457049
dblp:conf/date/HaoXRY10
fatcat:jpkqm3ucvfbfbeguuc4jvxyzuy
ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions
[chapter]
2019
Lecture Notes in Computer Science
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equivalence checking between different ILA models, and between an ILA specification and an implementation. ...
ILAng provides a programming interface for (i) constructing ILA models (ii) synthesizing ILA models from templates using program synthesis techniques (iii) verifying properties on ILA models (iv) behavioral ...
FSM behavioral equivalence checking using existing hardware verification tools. This pipeline case study is a simple version of the back-end of a pipelined processor. ...
doi:10.1007/978-3-030-17462-0_21
fatcat:eh2w44eg55forkmdlz2jud7abu
Scalable conditional equivalence checking: An automated invariant-generation based approach
2009
2009 Formal Methods in Computer-Aided Design
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Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades. ...
However, conditionally equivalent designswithin which internal equivalence may not exist under sequential observability don't care conditions -are notoriously difficult for automated SEC tools. ...
INTRODUCTION Equivalence checking refers to the process of demonstrating the behavioral input-to-output equivalence of two designs. Numerous equivalence checking paradigms exist in practice. ...
doi:10.1109/fmcad.2009.5351131
dblp:conf/fmcad/BaumgartnerMCSY09
fatcat:abtilmgzqzhplhpcf7pbpjngjy
Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis
2014
Electronic Proceedings in Theoretical Computer Science
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equivalence with automated sequential equivalence checking techniques. ...
Loop pipelining is one of the most critical and complex transformations employed in behavioral synthesis. ...
To certify a synthesized RTL with pipelines, it is sufficient to (1) check that our algorithm can generate a pipeline P for the parameters reported by synthesis, (2) use SEC to compare P with the synthesized ...
doi:10.4204/eptcs.152.10
fatcat:he3mzivs75eyjbfof6rovco7k4
Handling design and implementation optimizations in equivalence checking for behavioral synthesis
2013
Proceedings of the 50th Annual Design Automation Conference on - DAC '13
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We identify two key optimizations that complicate equivalence checking for behavioral synthesis: (1) operation gating, and (2) global variables. ...
Equivalence checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such equivalence checking must effectively handle design and implementation optimizations. ...
We thank Disha Puri, Naren Narasimhan, and Jin Yang for advice and help. ...
doi:10.1145/2463209.2488878
dblp:conf/dac/YangRHX13
fatcat:q24coqkw7zbgtno7ztk4kppn6u
Avenir: Managing Data Plane Diversity with Control Plane Synthesis
2021
Symposium on Networked Systems Design and Implementation
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the cost of retargeting a control plane from one pipeline to another. ...
We have built a prototype implementation of Avenir using OCaml and Z3 and evaluated its performance on realistic scenarios for the ONOS SDN controller and on a collection of benchmarks that illustrate ...
Acknowledgments The authors wish to thank Andy Fingerhut for suggesting that we explore the idea of control plane synthesis, and for many helpful discussions as we developed Avenir. ...
dblp:conf/nsdi/CampbellHSCLRHP21
fatcat:mphekw2yjrebncbjmtak6e7ff4
RTL2RTL Formal Equivalence: Boosting the Design Confidence
2014
Electronic Proceedings in Theoretical Computer Science
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2014 pre-print arXiv:1407.6342v1 fatcat:jeczvtjcjjgd3fju25vc5jqi34
Formal Equivalence can be applied for proving functional integrity after design changes resulting from a wide variety of reasons, ranging from simple pipeline optimizations to complex logic redistributions ...
Modern Formal Verification (FV) techniques involving new methods of proving Sequential Hardware Equivalence enabled a new set of solutions for the given problem, with complete coverage guarantee. ...
We would also like to thank our design team members for the constant support provided. ...
doi:10.4204/eptcs.156.7
fatcat:dwzculj6pra75ox2giyf6get2u
Integrating formal verification and high-level processor pipeline synthesis
2011
2011 IEEE 9th Symposium on Application Specific Processors (SASP)
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As an integral part of the pipeline synthesis, our framework also emits SMV models for checking the functional equivalence between the output pipelined processor implementation and its input non-pipelined ...
The paper reports case studies of applying this integrated framework to synthesize and formally verify pipelined RISC and CISC processors. ...
Clarke from School of Computer Science at Carnegie Mellon, Scott Robinson from Intel, and our colleagues in the Computer Architecture Lab at Carnegie Mellon for their interaction and feedback. ...
doi:10.1109/sasp.2011.5941073
dblp:conf/sasp/NurvitadhiHKL11
fatcat:xrnee2lta5eexexddvf5ndr2di
Sequential Equivalence Checking for Clock-Gated Circuits
2014
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Sequential logic synthesis often leads to substantially easier equivalence checking problems, compared to general-case sequential equivalence checking (SEC). ...
This paper theoretically investigates when SEC can be reduced to a combinational equivalence checking (CEC) problem. ...
Bezman of Magma (currently, Synopsys) for conducting updated comparisons on industrial examples. ...
doi:10.1109/tcad.2013.2284190
fatcat:kcdckvp4jnbfdfrianpnpa7dgm
A System for Efficiently Hunting for Cyber Threats in Computer Systems Using Threat Intelligence
[article]
2021
arXiv
pre-print
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(2) a concise and expressive domain-specific query language, TBQL, to hunt for malicious system activities, (3) a query synthesis mechanism that automatically synthesizes a TBQL query from the extracted ...
Built upon mature system auditing frameworks, ThreatRaptor provides (1) an unsupervised, light-weight, and accurate NLP pipeline that extracts structured threat behaviors from unstructured OSCTI text, ...
This work was supported in part by DARPA N66001-15-C-4066 and the CLTC (Center for Long-Term Cybersecurity). ...
arXiv:2101.06761v2
fatcat:2jex56n3yndjpcerwvuvnh464u
Synthesizing fast, online-testable control units
1998
IEEE Design & Test of Computers
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To compare the hardware costs of the different implementations, Table 2 shows representative gate-level equivalents necessary for self-checking standard structures and self-checking bypass pipelines. ...
Therefore, we considered 6 check bits the maximum effort for online checking. ...
doi:10.1109/54.735925
fatcat:slwhpnlzpnebrmebn2pf4jdtny
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