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2019 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)  
), Jonathan Ta (University of Wisconsin-Madison), and Jing Li (University of Wisconsin-Madison) Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control 154 Gurshaant Singh Malik (University  ...  Chang (UCLA), and Jason Cong (UCLA) Session 4: Applications 1 π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization 100 Shuzhen Qin (Tianjin University), Qiang  ... 
doi:10.1109/fccm.2019.00004 fatcat:qku57w2j2vfs3kluykjmqfbzya

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Ye Lu, John McCanny, Sakir Sezer
2011 2011 21st International Conference on Field Programmable Logic and Applications  
A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented.  ...  The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing  ...  [4] presented a comparison between a time-multiplexed NoC and a packet-switched NoC with a Butterfly Fat Tree (BFTs) topology on FPGA.  ... 
doi:10.1109/fpl.2011.25 dblp:conf/fpl/LuMS11 fatcat:itdlmvmyibenrjtmhxk3dyc6ei

Explicit Communication and Synchronization in SARC

Manolis Katevenis, Vassilis Papaefstathiou, Stamatis Kavadias, Dionisios Pnevmatikatos, Federico Silla, Dimitrios Nikolopoulos
2010 IEEE Micro  
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible occurrence of events  ...  The on-chip network provides efficient communication among these configurable memories, using advanced topologies and routing algorithms, and providing for process variability in NoC links.  ...  We also thank, for their assistance in designing the architecture and their collaboration in the SARC project: Alex Ramirez, Georgi Gaydadjiev, Angelos Bilas, George Kalokerinos, George Nikiforos, Dimitris  ... 
doi:10.1109/mm.2010.77 fatcat:jzsphc2sqrgpfh6rxdgvuswv5y

Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

Evangelia Kasapaki, Jens Sparso, Rasmus Bo Sorensen, Kees Goossens
2013 2013 Euromicro Conference on Digital System Design  
These end-to-end paths do not require any dynamic arbitration, buffering, flow control, or clock synchronization, in the routers or the NIs.  ...  The implementations target both FPGA technology and 65 nm CMOS technology.  ...  I am grateful to both of them for their time and for the opportunities they have  ... 
doi:10.1109/dsd.2013.40 dblp:conf/dsd/KasapakiSSG13 fatcat:yzvmstcvkvgfnbm5wysn2ipray

On the Design of a Fault-tolerant Scalable Three Dimensional NoC-based Digital Neuromorphic System with On-chip Learning

Ogbodo Mark Ikechukwu, Khanh N. Dang, Abderazek Ben Abdallah
2021 IEEE Access  
This paper presents NASH a , a fault-tolerant 3D-NoC based neuromorphic system that incorporates as processing elements, lightweight spiking neuron processing cores (SNPCs) with spike-timing-dependent-plasticity  ...  As neuromorphic systems require high integration to form a functional silicon brain-like, moving to 3D integrated circuits (3D-ICs) with three-dimensional network on chip (3D-NoC) interconnect is a suitable  ...  the input ports, crossbar, swich allocator, arbiter and flow control.  ... 
doi:10.1109/access.2021.3071089 fatcat:cbume3oknba57mra4pgul6v25a

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

Amin Sarihi, Ahmad Patooghy, Ahmed Khalid, Mahdi Hasanzadeh, Mostafa Said, Abdel-Hameed A. Badawy
2021 IEEE Access  
They are interconnected using channels following a predefined topology structure such as 2D/3D mesh, butterfly, fat-tree, etc.  ...  Moreover, this method does not support credit-based flow control NoCs, and the accuracy depends on the length of the attacks.  ...  Authentication in NoCs: An attacker in an MITM attack takes control of the connection between two parties and makes them believe that they are communicating with each other.  ... 
doi:10.1109/access.2021.3100540 fatcat:fi3uboiwlvhzpottpgrep5nqvq

Myrmics: Scalable, Dependency-aware Task Scheduling on Heterogeneous Manycores [article]

Spyros Lyberis, Polyvios Pratikakis, Iakovos Mavroidis, Dimitrios S. Nikolopoulos
2016 arXiv   pre-print
We propose design choices, policies and mechanisms to enhance runtime system scalability for single-chip processors with hundreds of cores.  ...  Compared to MPI versions of the same benchmarks with hand-tuned message passing, Myrmics achieves similar scalability with a 10-30% performance overhead, but with less programming effort.  ...  Finally, OpenStream [42] offers another alternative to enhance the OpenMP tasking model to support data-flow parallelism, through the use of streams, which defines how the tasks produce and consume data  ... 
arXiv:1606.04282v1 fatcat:c4f7fllpgnctdcf5uxz2kwxuiu

Design and performance optimization of asynchronous networks-on-chip

Weiwei Jiang
2018
As a result, there has been significant recent interest in combing the notion of asynchrony with NoC designs.  ...  Since the NoC approach inherently separates the communication infrastructure, and its timing, from computational elements, it is a natural match for an asynchronous paradigm.  ...  For (ii), three topologies are includedvariant Mesh-of-Trees, Fat Tree and Flattened Butterfly. 2D Mesh-Based Topology A 2D mesh-based topology is a direct network, where each router (i.e. switch) in  ... 
doi:10.7916/d8rf7b21 fatcat:tvsdrghsyffcpcb6u7xzx54nyq

2012 WVAS abstracts

Joseph Horzempa
2016 Proceedings of the West Virginia Academy of Science  
Abstracts for the 2012 WVAS meeting  ...  This research presents some possible realistic NoC designs using a three dimensional design architecture for Fat-Tree Butterfly (FTB), Extended FTB, and Enhanced FTB.  ...  Many fat-tree interconnectivity designs for network-on-chip (NoC) are unrealistic and impractical to implement due to physical chip design limitations.  ... 
doi:10.55632/pwvas.v84i1.148 fatcat:fbc3ctpxing3hen2hmjkbrm77q

D8.3.2: Final technical report and architecture proposal

Ramnath Sai Sagar, Jesus Labarta, Aad van der Steen, Iris Christadler, Herbert Huber
2010 Zenodo  
This document describes the activities in Work Package 8 Task 8.3 (WP8.3) updating and analysing results reported in D8.3.1 for the different WP8 prototypes.  ...  The document also suggests potential architectures for future machines, the level of performance we should expect and areas where research efforts should be dedicated.  ...  The alternative approach of using the Memory Flow Controller (MFC) of an SPE instead of modifying the FPGA image has not (yet) been implemented.  ... 
doi:10.5281/zenodo.6546134 fatcat:35eigjqrzvb3vfd3pjud2oswtu

Mapping and management of communication services on MP-SoC platforms [article]

Marescaux, TM (Théodore), Corporaal, H (Henk), Verkest, DTML (Diederik)
2007
Dummy packet dropping is not required for SuperGT to function, but is an enhancement we have implemented in our SuperGT NoC model. it receives, an end-to-end credit-based flow-control scheme is used per  ...  To this end it uses aggressive techniques: it uses a fat-tree topology (32-bit links) to minimize the network diameter, uses VCT switching and 4-phits flits for deeper pipelining (Figure 3 .20).  ...  The StrongARM processor present inside a Compaq iPAQ PDA is linked to an FPGA that contains 8 slave processors interconnected by two NoCs (control and data).  ... 
doi:10.6100/ir629360 fatcat:e5kz6vvr7fguldjhdpjyge3u34

Interconnection systems for highly integrated computation devices

Federico <1978> Angiolini, Luca Benini
2008
However, as with any technology of recent inception, NoC design is still an evolving discipline.  ...  Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the  ...  In some proposed NoC architectures, flow control is combined with error control in a unified mechanism.  ... 
doi:10.6092/unibo/amsdottorato/931 fatcat:d6uz2egvvfd4lgjwvnadzjjdra

Photonic Interconnects Beyond High Bandwidth

Ke Wen
2017
Simulations with applications such as GTC, Nekbone and LULESH show up to 1.8x speedup over Dragonfly paired with UGAL routing, along with halved hop count and latency for cross-group messages.  ...  It can steal additional direct bandwidth for communication-intensive group pairs.  ...  In these designs, the memory interface works as an endpoint on the NoC: instead of a NoC tile with a processor core, it is a NoC tile with a memory controller.  ... 
doi:10.7916/d8kw5gm1 fatcat:3xlkp7lszvclplsq25cp54uxwu

Network-Compute Co-Design for Distributed In-Memory Computing

Alexandros Daglis
2018
I could not have asked for better parents, and for that I am extremely fortunate and grateful. My dearest brothers, Thanasis and Dimitris, have been the best company to grow up with.  ...  You have been my safe haven, inspiration and joy for the past decade, and I am looking forward to spending a lifetime with you. I love you.  ...  Rea, for her friendship,  ... 
doi:10.5075/epfl-thesis-8749 fatcat:ualgpsobv5bepfyuc65ag536r4