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Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
2007
2007 International Conference on Field Programmable Logic and Applications
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In the reconfigurable logic, general-purpose finegrained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are ...
This paper presents a novel architecture for domain-specific FPGA devices. ...
Acknowledgements The authors gratefully acknowledge the support of the UK EPSRC (grant EP/C549481/1 and grant EP/D060567/1). ...
doi:10.1109/fpl.2007.4380647
dblp:conf/fpl/HoYLLW07
fatcat:r3bmzlcugfcz5dgd66fkyj2yv4
Optimizing coarse-grained units in floating point hybrid FPGA
2008
2008 International Conference on Field-Programmable Technology
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This paper introduces a novel methodology to optimize coarse-grained floating point units (FPUs) in a hybrid FPGA. ...
We derive an optimized coarse-grained FPU by considering both architectural and system level issues. ...
The support of UK Engineering and Physical Sciences Research Council (EP/C549481/1, EP/D060567/1 and EP/D062322/1) and Canadian Commonwealth Postdoctoral Fellowship scheme (Canadian Bureau for International ...
doi:10.1109/fpt.2008.4762366
dblp:conf/fpt/YuSLLW08
fatcat:gk7dhmqpv5c5lkzbtfvfvrigmu
Intermediate fabrics
2010
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES/ISSS '10
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lack of portability and interoperability resulting from device/platform-specific tools and bitfiles. ...
to several problems: 1) difficulty of integrating hardware design tools into well-established software tool flows, 2) increasingly lengthy FPGA design iterations due to placement and routing, and 3) a ...
The authors gratefully acknowledge vendor equipment and/or tools provided by Altera, Nallatech, and Xilinx. ...
doi:10.1145/1878961.1878966
dblp:conf/codes/CooleS10
fatcat:qo5tbdd5xfchhh4i63djiexkae
Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices
2006
2006 International Conference on Microelectronics
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finite grain instruction set extensions in application code and granularity level. ...
Our goal is to generate a prototype of reconfigurable for providing enhanced performance in SoC. ...
Jha, "A scalable application-
granularity levels:
specific processor Execution time
Power
Resources usage
tool for evaluating and synthesizing multimedia and communications
(pts)
dissipation
(Stratixll ...
doi:10.1109/icm.2006.373284
fatcat:wjhslqgydnbm7cods2l3htghny
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs
2016
2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
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This paper presents fpgaConvNet, a novel domain-specific modelling framework together with an automated design methodology for the mapping of ConvNets onto reconfigurable FPGA-based platforms. ...
A comparison with existing ConvNet FPGA works shows that the proposed fully-automated methodology yields hardware designs that improve the performance density by up to 1.62× and reach up to 90.75% of the ...
With FPGAs' size and resource specifications changing at a fast pace, there is a need for tools that abstract the hardware resource details of a particular FPGA-based platform and guarantee portability ...
doi:10.1109/fccm.2016.22
dblp:conf/fccm/VenierisB16
fatcat:w5u3nv2id5fdxd34fgvffvpnma
Customizable Domain-Specific Computing
2011
IEEE Design & Test of Computers
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We believe that there is significant opportunity to look beyond parallelization and focus on domain-specific customization to bring orders-of-magnitude power/performance efficiency improvement to important ...
Therefore, it is possible to develop a customizable computing platform in which computing engines and interconnects are specialized for that particular application domain, gaining significant improvements ...
Acknowledgments The Center for Domain-Specific Computing is funded by the National Science Foundation's Expedition in Computing Award CCF-0926127. ...
doi:10.1109/mdt.2010.141
fatcat:vha5ip7aifhmpfug24xmpol6fi
Customizable domain-specific computing
2009
2009 International Conference on Field Programmable Logic and Applications
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We believe that there is significant opportunity to look beyond parallelization and focus on domain-specific customization to bring orders-of-magnitude power/performance efficiency improvement to important ...
Therefore, it is possible to develop a customizable computing platform in which computing engines and interconnects are specialized for that particular application domain, gaining significant improvements ...
Acknowledgments The Center for Domain-Specific Computing is funded by the National Science Foundation's Expedition in Computing Award CCF-0926127. ...
doi:10.1109/fpl.2009.5272570
dblp:conf/fpl/Cong09
fatcat:7s3eipjl3fhpbe7o3scdljnc44
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
[chapter]
2000
Lecture Notes in Computer Science
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Coarse-grain reconfigurable architectures promise to be more adequate for computational tasks due to their better efficiency and higher speed. ...
/ power trade-off for a given application domain. ...
Coarse grain reconfigurable Xputer Lab architectures avoid several drawbacks of FPGAs. ...
doi:10.1007/3-540-45373-3_12
fatcat:fqupauzbcne5haq4dhqbfm7l5a
Latency-driven design for FPGA-based convolutional neural networks
2017
2017 27th International Conference on Field Programmable Logic and Applications (FPL)
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This paper presents a latency-driven design methodology for mapping ConvNets on FPGAs. ...
In this context, FPGAs can provide a potential platform that can be optimally configured based on different performance requirements. ...
Each architecture is specifically optimised for the particular subgraph and can utilise all of the FPGA resources. ...
doi:10.23919/fpl.2017.8056828
dblp:conf/fpl/VenierisB17
fatcat:mhqwbqws25dzbasngtdtl5dqoq
A Framework for Compiler Driven Design Space Exploration for Embedded System Customization
[chapter]
2004
Lecture Notes in Computer Science
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This paper presents compiler directed design space exploration as a framework for articulating, formulating, and implementing global optimizations for embedded systems customization, where the design space ...
For this trend to continue, we must find ways to overcome the twin hurdles of rising non-recurring engineering (NRE) costs and decreasing time-to-market windows by providing major improvements in designer ...
Coarse grained "sea of tiles" architectures, though not as flexible as fine grained FPGAs greatly reduce power, area, delay and configuration times. ...
doi:10.1007/978-3-540-30502-6_29
fatcat:aeceqkskxngnjjlbp4n247mcyi
Reconfigurable computing: architectures and design methods
2005
IEE Proceedings - Computers and digital Techniques
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It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications. ...
The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. ...
enable both high-level design and domain-specific optimisation. ...
doi:10.1049/ip-cdt:20045086
fatcat:rz53tnd6yfd7heyk5qhvaj5jfu
Domain Adaptive Processor Architectures
[chapter]
2020
Technologien für die intelligente Automation
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A novel class of processors which provide more data throughput with a simultaneously tremendously reduced energy consumption are required as a backbone for these "Things". ...
This paper shows a brief overview of novel processor architectures providing high flexibility to adapt during design-and runtime to changing requirements of the application and the internal and external ...
Many different approaches for coarse-grained compute architectures have been proposed, most of them suited for specific workloads and providing significant speedups. ...
doi:10.1007/978-3-662-59895-5_23
fatcat:c3rzfowftfh4ncjxsjsgzbpy4a
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge
[article]
2019
arXiv
pre-print
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for explored DNNs. ...
In this paper, we propose a simultaneous FPGA/DNN co-design methodology with both bottom-up and top-down approaches: a bottom-up hardware-oriented DNN model search for high accuracy, and a top-down FPGA ...
ACKNOWLEDGMENTS This work was partly supported by the IBM-Illinois Center for Cognitive Computing System Research (C 3 SR) -a research collaboration as part of IBM AI Horizons Network. ...
arXiv:1904.04421v1
fatcat:s4ozvvz5kbd2zk4iynjecqiljm
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators
2019
IEEE Embedded Systems Letters
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Domain-specific acceleration is now a "must" for all the computing spectrum, going from high performance computing to embedded systems. ...
Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow models of computation with Coarse-Grained Reconfigurable (CGR) architectures ...
Many HLS tools are now available, such as Xilinx Vivado HLS [17] and Intel FPGA SDK for OpenCL [4] . These tools are based upon imperative, C-like, languages. ...
doi:10.1109/les.2018.2882989
fatcat:uh7mhmyw4bh4xciykwb6bnepgy
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip
2002
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02
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We explore the standard cell method, as well as the creation of FPGA-specific standard cells. ...
When designing SOCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. ...
We also are indebted to Larry McMurchie for support on the Cadence tool-suite. The idea for using standard cells to implement FPGA architectures was originally proposed by Herman Schmit. ...
doi:10.1145/503070.503073
fatcat:vtoip256zjhf5gldbeqmhowyfy
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