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Energy-efficient skewed static logic with dual Vt: design and synthesis
2003
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this paper, we describe skewed static logic ( 2 ) with topology-dependent dual which exhibits an energy-efficient operation. 2 consumes less dynamic and static power compared to monotonic static (MS ...
We have also designed 32-b carry-lookahead adders and verified that 2 with dual reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. ...
SKEWED STATIC LOGIC WITH DUAL We propose skewed static logic ( ) circuits based on previous analysis. ...
doi:10.1109/tvlsi.2002.800528
fatcat:kecavtghbvflxbqykk6tgkhaay
Logic Synthesis
[chapter]
2017
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology
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Davoodi, A parallel and randomized algorithm for large-scale dual-Vt assignment and continuous gate sizing, Proceedings of International Symposium on Low Power Electronics and Design, Bangalore, India, ...
During the invention era, logic synthesis, placement, routing, and static timing analysis were invented. ...
doi:10.1201/9781315215112-13
fatcat:me52zpnxyfcczh3choo2p4zulm
Sub-90nm technologies
2002
Computer-Aided Design (ICCAD), IEEE International Conference on
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Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. ...
Design practice will have to change from deterministic design to probabilistic and statistical design. ...
However, with the power constraints emerging as paramount, future microarchitectures will incorporate specialpurpose functionality to improve the benchmark performance in a more area and energy-efficient ...
doi:10.1145/774572.774602
dblp:conf/iccad/KarnikBD02
fatcat:5dbe625kd5d7rlxd2c7fhcbqti
Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips
2020
Journal of Low Power Electronics and Applications
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Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches ...
Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale ...
The low-VDD global clock distribution network on the NTV-CPU (Figure 11c ) is designed with low-VT devices to minimize clock skew across logic and memory voltage domain crossings, across the entire operating ...
doi:10.3390/jlpea10020016
fatcat:wuwirnk4ljc7tjllpzc3ng7jei
High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic
2002
IEEE transactions on circuits and systems - 2, Analog and digital signal processing
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PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. ...
Our experimental results on two 32-bit carry lookahead adders using 0.25-m CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by ...
We propose a new parallel dynamic logic and speed-enhanced skewed static gates that use accelerators to enhance the speed of skewed static gates. This paper is organized as follows. ...
doi:10.1109/tcsii.2002.802960
fatcat:p22jqi46kzblznwry3qf5lnqei
Area-efficiency in CMP core design
2009
SIGARCH Computer Architecture News
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tuned dual-issue 4-way multithreaded design running at a lower frequency. ...
In this paper, we examine the area-performance design space of a processing core for a chip multiprocessor (CMP), considering both the architectural design space and the tradeoffs of the physical design ...
The choice of circuit style is another parameter in the implementation design space. Static CMOS circuits save energy, but are slower than dynamic and differential logic styles. ...
doi:10.1145/1577129.1577138
fatcat:bpp3llavirhf3oe5the7r6qcji
Practice Problems for Hardware Engineers
[article]
2021
arXiv
pre-print
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2021 pre-print arXiv:2110.06526v2 fatcat:qg3wlnsaszannnuylumg3n342uOther Versions
It may also be used as a practice resource while taking courses in VLSI, logic and computer architecture design. ...
This book is to help undergraduate and graduate students of electrical and computer engineering disciplines with their job interviews. ...
Draw a domino CMOS logic circuit that realizes W or W' whichever more convenient for you to design. Design a dual rail Domino logic for W. ...
arXiv:2110.06526v3
fatcat:hquxq53eqrcetlsgwa7i34wsri
A Low-Power Integrated x86–64 and Graphics Processor for Mobile Computing Devices
2012
IEEE Journal of Solid-State Circuits
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, a media accelerator, an integrated NorthBridge (NB), integrated DisplayPort, LVDS, and VGA display interfaces, a PCIe ® Gen1 or Gen2 I/O interface, and a single 64-bit memory channel at up to DDR3-1066 ...
The first AMD Fusion™ accelerated processing unit (APU), code-named "Zacate," incorporates a pair of Bobcat x86 processors, a 1 MB L2 cache, an AMD Radeon™ 6310 DirectX ® 11 GPU with 80 stream processors ...
The fully OoO design with deep speculation enables energy saving by keeping the pipeline filled while reducing dynamic and static energy spent on stalled cycles as well as significantly increasing IPC ...
doi:10.1109/jssc.2011.2167776
fatcat:c7lyh6gemfbenokg5ybdnt47la
Quantitative Characterization of Reconfigurable Transistor Logic Gates
2020
IEEE Access
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Besides worst-case analysis, we leverage measures hardly accessible to simulation such as average delay and average energy consumption per switching operation. ...
We complement this with an automated design-space exploration that yields all reasonable implementations of a switching function built with reconfigurable transistors. ...
Most power / energy efficient circuit but sensitive to input distribution, (4i) Semi-static, reconfigurable via input A. ...
doi:10.1109/access.2020.3001352
fatcat:rjy2uq2a5ndb7i26d7eaklutmu
Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices
2005
IEEE Transactions on Electron Devices
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An efficient circuit synthesis methodology comprised of proposed low-power logic options in FinFET design library has been developed. ...
In this paper, we developed semianalytical delay and power models for IG FinFET-based logic cells, and a generic efficient design library-based circuit synthesis framework. ...
/FinFET devices, for high-performance logic and memory applications. ...
doi:10.1109/ted.2004.842713
fatcat:ki5vlrqvczegnnbc6kuszrxzky
Error Estimation and Error Reduction with Input-Vector Profiling for Timing Speculation in Digital Circuits
2018
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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To further enhance the performance and energy efficiency of BTWC designs, a rigorous analysis of path activation probability across a typical workload of the design would provide insight that helps the ...
Figure 3 shows an example of dynamic behavior, where A and B are two logic paths of a circuit with the same static delay time. ...
Figure 31 : The flow chart of the Extract and Compare script's algorithm. ...
doi:10.1109/tcad.2018.2808240
fatcat:rfrozu53jjd5pntinkjfieklpq
Benefits of decomposing wide CMOS transistors into minimum-size gates
2009
2009 NORCHIP
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enhanced understanding, and improved methods for the purpose of designing reliable and efficient subthreshold digital logic and memory. ...
Sense amplifier design in the subthreshold domain is perhaps the most challenging task of ULV SRAM design as RDF causes severe mismatch in the input sensing transistors, and speed and energy efficiency ...
doi:10.1109/norchp.2009.5397795
fatcat:rr6gli6uxngtxfzm5zk2t5azfq
Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment
2012
Foundations and Trends® in Electronic Design Automation
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Concepts such as standard cell libraries, static timing analysis, and analytical delay and power models are explained, along with examples and data to help understand the tradeoffs involved. ...
The gate widths and threshold voltages, along with the gate lengths, can be adjusted to optimize power and delay. ...
Andrew Kahng and Dr. Kwangok Jeong for their help with the post-layout timing, Amarnath Kasibhatla for his support with the eyecharts, and Santiago Mok for his support with the UCLA Timer. ...
doi:10.1561/1000000019
fatcat:gtyz4bhlxvetppbvxbhum2sioy
Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things
2017
Electronics
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Asynchronous circuits connect multiple components effectively across a large die for energy efficiency. ...
Clearly, energy efficient mobile computing requires an ultra-low-power system design [18] . Achieving a very low average power for a wireless system typically makes extensive use of duty cycling. ...
Author Contributions: Jiann-Shiun Yuan organizes the materials and writes the manuscript. Jin Lin contributes to low power SAR ADC and hybrid ΔƩ SAR ADC designs. ...
doi:10.3390/electronics6030067
fatcat:ozssarlb2ng5pcdsupo2hljyna
Design, Automation, and Test for Low-Power and Reliable Flexible Electronics
2015
Foundations and Trends® in Electronic Design Automation
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We will then give an overview of digital and analog circuit design from basic logic gates to a microprocessor, as well as design automation tools and methods, for designing flexible electronics. ...
, large process variation, and lack of trustworthy device modeling also make designing larger-scale and robust TFT circuits a significant challenge. ...
It begins with the design modeling and verification loop, which continues until the design model processes the necessary details, ex. the register-transfer-level (RTL) design, to proceed to logic synthesis ...
doi:10.1561/1000000039
fatcat:n6vf2kzcprbt7aojy6u74inkui
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